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LMK04832: PLL Looses Lock with a 10 MHz signal

Tyler Gibson
Prodigy 10 points
Part Number: LMK04832

Hello Team!

We are utilizing TICS configuration attached below. We are operating in CLKin_Sel_Manual mode and able to obtain a lock on CLKin0 (10MHz) on power on but loose lock 30-60s after startup and are unable to reacquire the signal with holdover disabled. The input is a 10 MHz LVDS fed from an external source. With our configuration, CLKin1 is able to maintain signal lock (different 10 MHz source). To clarify we are loosing DLD on PLL1, PLL2 continues to hold DLD.

Register 0x183 reports 0x09
Register 0x184 reports 0x48
Register 0x185 reports 0xCD
Register 0x188 reports 0x41

Just looking for some insight on our configuration.

Dual_Loop.tcs

  • 0
    TI__Mastermind 33370 points

    Tyler,

    If PLL2 remains locked, but PLL1 is becoming unlocked, this usually suggests an issue with the reference or the loop stability.

    • Are you using the same loop filter as the default loop filter on the LMK04832EVM? For 100MHz VCXO and 1MHz phase detector this may not be stable; you could quickly check if you have better luck with Kpd = 0.25mA instead of 0.45mA to see if loop stability is impacting the result.
    • If not, you can try configuring the STATUS_LD1 and STATUS_LD2 pins to mirror the inputs to the phase detector of PLL1, and monitor them on an oscilloscope to observe what's happening at the phase detector. This may give you a clue in case the input reference is being corrupted for some reason.
    • You can also probe the CPout1 pin with an oscilloscope and check the charge pump voltage leading up to and during the loss of lock event, as the pattern of how the device loses lock may be a clue.

    Regards,

    Derek Payne

  • +1 in reply to Derek Payne
    Prodigy 10 points

    Hi Derek,

    Thanks for the quick reply!

    We are using the default loop filter found on the LMK04832EVM Board. A quick drop of the kpd to 0.25mA had no effect. I will be poking around our board tomorrow but I have a feeling our loop bandwidth is too small for the  deviation in our incoming RF signal. We have designed a higher bandwidth loop filter using the PLLatinumSim software, that will hopefully do the trick.

    What are your thoughts on the increasing the 1MHz phase detector frequency to 5MHz?

    Cheers,

    Tyler

  • 0 in reply to Tyler Gibson
    TI__Mastermind 33370 points

    Tyler,

    Okay, that makes sense - if your input clock is deviating and the loop filter is too small to track the deviation, reducing Kpd would reduce the bandwidth and probably make the problem worse.

    At 5MHz PFD frequency, assuming a VCXO gain that's comparable to the EVM's default VCXO gain, the default loop filter will be unstable. I recommend using PLLatinum Sim to determine a filter that has at least 45° phase margin (phase margin calculation becomes available in either intermediate or advanced feature level). It's definitely a test worth trying.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    TI__Genius 12560 points

    Hi Tyler,

    We haven't heard long time from you and assumed you may have resolved the issue with above suggestions.

    I am closing this thread and feel free to write again on the same thread or open new for further support.

    Thanks!

    Regards,

    Ajeet Pal