I've been reading through the datasheet of the LMK03318 and have come across this little note which refers to the LVCMOS PRIREF input pins.
The oscillator we are planning to use has a input low voltage of 0.33V maximum, this won't require the slew-rate detect circuitry to be enabled right? Due to the input high voltage being 3.3V, thus exceeding the 1.7V.
Another question I have is regarding the Webench tool to simulate this chip. I've read through alot of forums on this website where people use the Webench tool to simulate this chip, however I cannot find that exact tool anymore. Has this turned into the more basic Clock Tree Architect? We'd love to simulate our reference oscillator together with this PLL to see how it would perform as we are unsure if the specified phase noise and rms jitter would be too much for the PLL.
