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CDCVF2510: CDCVF2510

Part Number: CDCVF2510
Other Parts Discussed in Thread: CDCE706, CDCE6214

Hi

I am using the CDCVF2510 at Vcc=2.5V to generate a clock to a FPGA

The FPGA requires that this clock will have a Trise of up to 500pS (10%-90%)

Looking at the CDCVF datasheet I see it has at Vcc=2.5V Tr minimum slewrate is 0.5V/nS. This will sum

at a rise from 0.4V to 1.7V to almost 3nS !!

With such Tr , there is no way to reach the promised Fmax of 170Mhz (5.9nS)

Even if I look at best slewrate (1.4V/nS) I am facing Tr of about 1nS, still far from the FPGA required 500pS.

Are my calculations are correct and the CDCVF best Trise at Vcc=2.5V is merely 1nS ?

If so, is there another clock generator (x5 as minimum fanout) that can meet the FPGA requirement?

Any suggestion how to improve my timing will be appreciated

Thanks

Amnon

  • Hi Amnon,

    Its pretty much old part and while looking in datasheet, rise time should be 0.3 ns (not ns/V) with this slew rate should be ~5V/ns. To have the FPGA required rise time, I believe its slew rate is on edge and I would suggest to look on CDCE6214 (x4 fanout) or CDCE706 (x6 fanout).

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Ajeet

    Thanks a lot for the prompt answer.

    I am sorry but I failed to find in the CDCVF2510 datasheet the values you have mentioned in your answer.

    Can you point me please to the exact section where you see in the datasheet Trise of 0.3nS

    or slewrate of 5V/nS?

    If these are figures that are calculated from other values please specify the math you have made to reach these values

    I understand that to rise a ramp of 1.5 (1.7V -0.2) at 5V/nS slewrate will last 0.3nS, but as I wrote before I didn't see 0.3nS nor 5V/nS at the datasheet...

    Looking forward to hear from you

    Thanks

    Amnon

  • Hi Amnon,

    Here is a link for CDCVF2510 datasheet

    You can look for the rise time specs shown in electrical specs table.

    Thanks!

    Regards,

    Ajeet Pal