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LMK04826: Synchronization between SYSCLK and SYSREF

JH Shin
Guru 11270 points
Part Number: LMK04826


Hello,

My customer is using the LMK04826 with the settings in the following config file.

lmk04826_220225.tcs

Whenever they initialize the LMK04826, there is a difference in synchronization between SYSCLK and SYSREF as shown below.

Please review the device settings to ensure consistent synchronization between SYCLK and SYSREF at all times.

Thank you.

JH

  • 0
    TI__Mastermind 33860 points

    Hi JH,

    Right now, no synchronization is being applied, and the divider states for the outputs are initialized according to the SPI timings which will vary considerably. Does the customer also have a synchronization procedure?

    I notice they have SYNC_PLL2_DLD enabled. If they want PLL2 lock to generate the divider reset and the SYNC signal, they first have to configure the SYNC path to accept PLL2_DLD as a SYNC source (SYNC_MODE = 1, SYSREF_MUX = 0) and initially must program the device with SYNC_DISx = 0 and DDLY_PD = 0 for all dividers participating in synchronization. Initially the output clocks will be held in reset, then when PLL2 locks the reset condition will be released. Finally, they can switch SYSREF_MUX to the desired setting after PLL2_DLD asserts.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Guru 11270 points

    Hi Rayne,

    Thanks for your reply.

    The customer believes that the two clock signals generated inside the LMK04826 should be synchronized with each other even if the SYNC pin is not used.

    Is it correct to use the SYNC pin to synchronize the LMK04826 internal clock as well?

    Is there a way to synchronize the LMK04826 internal clocks including SYSREF by S/W control without using the SYNC pin?

    Regards,

    JH

  • 0 in reply to JH Shin
    TI__Mastermind 33860 points

    JH,

    The SYNC_PLL2_DLD pin is OR'd together with the input from the SYNC pin. The method I described above does not involve using the hardware SYNC pin at all, and happens completely in software.

    Regards,

    Derek Payne

  • 0 in reply to Derek Payne
    Guru 11270 points

    Hi Payne,

    After the customer changed the initialization sequence, the random synchronization becom fairly consistent.

    However, fluctuations are observed in the range of about 400ps. Is this normal?

    Can it be changed in about one cycle of VCO?

    Regards,

    JH

  • 0 in reply to JH Shin
    TI__Mastermind 33860 points

    JH,

    400ps error sounds like one VCO cycle of difference between synchronizations. Since all the fixed digital delays should be reset in the device clocks whenever the SYNC event occurs, the only place I could imagine there being an issue is in the SYSREF. Maybe they can try programming the device with SYSREF_CLR=1 initially, then after lock is acquired they can clear SYSREF_CLR=0 in the same programming update as clearing SYNC_PLL2_DLD=0. The SYSREF local digital delays on each channel have a separate clearing mechanism from the fixed digital delay, which may be responsible for the VCO cycle of difference between power cycles.

    Regards,

    Derek Payne