LMK04832: Timing requirement

Rayna,

A few thoughts before we provide timings:

• Pin-mode reset and register reset perform the same function, so the easiest way to ensure POR is setting the RESET bit in R0 during initial register configuration. The reset is guaranteed to happen within the time taken for a single SPI write.
• There are several features such as SYNC_PLL1_DLD and SYNC_PLL2_DLD which can automate the synchronization procedure so it occurs automatically whenever PLL1 or PLL2 locks respectively.

Now, if the customer is going to generate pin reset and SYNC regardless:

T1: min time = 0. RESET pin can be pulled up with power if desired.

T2: min time = 1µs. We expect the reset to occur within maybe four or five state machine clock cycles, and the state machine clock within LMK04832 is running at 10MHz ± 30%, so 1µs is a safe bet.

T3: min time = 0. Register configuration can occur immediately after RESET pin goes low. SPI communication is slower than state machine clock.

T4: min time = depends entirely on application settings and time for PLL to lock. The SYNC pulse should not be generated before the PLL locks. In principle the SYNC pulse can be generated at any time as long as there is a clock distribution path signal (e.g. the VCO is up and running). In practice there are some configurations which loopback the SYSREF divider as a feedback divider in zero delay mode, and ideally the divider reset should only occur after the PLL locks (especially if the SYNC is re-timed to the SYSREF divider). If there is no input-to-output phase alignment requirement on LMK04832, min time for T4 = 0 and SYNC event can be handled by pin or by software automatically. If there is an input-to-output phase alignment requirement depending on the SYSREF divider in feedback to one of the PLLs, min time for T4 is however long it takes for the PLL with SYSREF divider feedback to lock.

T5: min time = depends entirely on application settings.

• When SYNC is retimed to clock distribution path divider alone, the minimum time is maybe 5ns + 1 clock distribution path period - there is maybe 5ns max propagation delay in SYNC pin circuit to the clock distribution retimer, and the clock distribution edge must go high at least once to generate the SYNC signal. The SYNC signal must remain high for eight clock distribution path cycles, or we can enable SYNC_1SHOT_EN and the SYNC pulse need only last for 5ns + 1 clock distribution path cycle (the one-shot will fire for the required duration of the SYNC event). 
• When SYNC is retimed to the SYSREF divider or in pulser mode, the minimum time is 5ns + 1 SYSREF period. Technically if the phase of the SYSREF is known, the total time can be reduced - as long as the SYSREF edge clocks in the SYNC event, the event only needs to last 1 clock distribution path period longer than the time from SYSREF edge going high internally. In practice the exact phase of the SYSREF within the SYNC system is not known and there are delays between the internal SYSREF retimer and the output which may make the phase difficult to predict, so generating a truly minimal SYNC pulse is challenging; In practice, waiting a few nanoseconds after the SYSREF rising edge is sufficient.
• If the SYNC is retimed to clock distribution path divider AND SYNC signal is generated by CLKin0, this signal only needs to last for one clock distribution path period (with SYNC_1SHOT_EN) or 8 clock distribution path periods (without SYNC_1SHOT_EN). The CLKin0 path timing is very precise and is made from bipolar transistor circuit elements, unlike the slower SYNC pin which is made from MOS transistor elements with much larger variable delays across PVT. Consequently, CLKin0 pulses can be much shorter.
• There isn't really an upper limit on the SYNC pulse timing. It can last as long as it needs to for convenience or ease of generating the pulse.

Regards,

Derek Payne