LMK05318B: Using the LMK5318B part and having problems getting the DLL to lock

Hi Danilo,

Is this issue the same as below?

(+) LMK05318B: Cascade devices - Clock & timing forum - Clock & timing - TI E2E support forums

Thanks!

Regards,

Ajeet Pal

Hi Ajeet,

According to our customer,

The issue is similar but not the same. 

In the first issue we were feeding the PRIREF from a single ended source. The single ended source was driven from 1.8V logic and the waveform was distorted at the input even though we had a 33 ohm series terminator at the source. We looked at the spec and tried driving from a 2.5V logic source without success. When we removed the 33 ohm terminator and replaced it with 0 ohm the waveform at the LMK05318b cleaned up and the chip started locking. We weren’t exactly thrilled with the solution but had spent more than enough time on that issue and needed to move on. The plan is to return to the problem and do more diagnostic, possibly redesigning the interface. 

The new problem is the same chip in a different position in the design. This time the PRIREF is driven from the ACLVDS output from the first with a 100 ohm diff term and series caps at the chip input similar to what is recommended by TI clock buffers. The signal is 156.250MHz and is driven over 14” of Meg 6 as a diff pair. One high speed connector is in line.  We debugged one board and got it working by removing the 100 ohm diff term from the board. When trying to bring up a second board we cannot get the same configuration file to get DPLL Phase or Frequency lock.  The waveform at the PRIREF input is clean and approximately 1.6V differential.

 Both designs  XO inputs are driven by the same 48.0048MHz osc that the TI demo board uses. Since the XO input does not feed the DPLL we only looked at the XO input to verify the waveform is reasonable. 

We tried rebuilding the files used from scratch issuing the default config in the tool. This improved some issues in the first design but has not impacted the second. 

It shouldn’t be this hard to get lock in your chip. Please provide some guidance. I’ve been in contact with the local TI rep, Eric Szyper, and sent him our configuration file.

Regards,

Danilo

Hello Danilo,

I apologize for your difficulties, I agree you shouldn't have so much issue.  I will check with Eric and get the TCS file to see what I can find.

73,
Timothy

Hi Timothy,

According to our customer,

On the previous case I provided a schematic for the input. I’m not sure which of the two designs it was. If you need any other information please ask.

 Schematic digram.zip

Also do you have an example design other than the Demo board schematic I can use as a reference to review our implementations?

Regards,

Danilo

Hi Danilo,

I don't have another design example - but I will check for some other design assist material.

73,
Timothy