LMK04832: Register setting Review.

Hiroaki Yuyama TED

Part Number: LMK04832

Dear, Support Team.
I have a Register setting question.

We are evaluating LMK04832 on a prototype board. ..
We changed the setting of VCO0 in the frequency range of 2560MHz.
When I checked it on the actual machine, the expected value was 80MHz, but the measured value was 83.453MHz.
I would like some advice on why it does not reach 80MHz.
I will attach a file of our register settings.
LMK04832_TED_0401_00.tcs

Best Regards,
Hiroaki Yuyama

over 3 years ago

0 Ajeet Pal over 3 years ago

TI__Genius 12560 points

Hi Hiroaki-san,

There could be reason of not PLL lock and getting default frequency out. PLL2_N_CAL value should be same as PLL2_N value, as device uses the PLL2_N_CAL value during frequency calibration.

Can you check the PLL1 and PLL2 are locking or not?

You can try with the update .tcs file and see the performance.

LMK04832_TED_0401_00_updated.tcs

Thanks!

Regards,

Ajeet Pal

0 Hiroaki Yuyama TED over 3 years ago in reply to Ajeet Pal

Expert 1740 points

Hi Ajeet-san,

Thank you very much for your advice and updating the register settings.
I update the register settings to check if PLL1 and PLL2 are locked.
I will tell you the result of the update again.

Best Regards,
Hiroaki Yuyama

0 Hiroaki Yuyama TED over 3 years ago in reply to Hiroaki Yuyama TED

Expert 1740 points

Hi Ajeet-san.

Thank you very much for your advice and updating the register settings.
I changed it to your register setting and changed the external CLK In from DC to AC input and it worked fine!
We normally locked the PLL and eliminated the deviation of the frequency division setting.
The cause was that the Lo level and Hi level of DC CLK In were out of the specifications of the data sheet.

Best Regards,
Hiroaki Yuyama

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LMK04832: Register setting Review.