Hi, I am programming LMX2820 registers over SPI using an FPGA. In an effort to load them as fast as possible, I am sending register data one after another while holding CS# low during the transfers. After 16 bytes, my FIFO empties and while it is being refilled with more data, I hold the clock high. Because each transfer is 3 bytes, I get 5 transfers and then only the address of the 6th register is sent while I hold the clock until the remaining data is ready to send.
About 28 microseconds later, the transaction continues where it left off, with the clock restarting:
This does not seem to work (PLL does not lock) even after seeing all SPI transfers complete with correct data. Whereas, sending data in discrete blocks of 3 bytes (one register at a time) does work:
Clock rate is only around 10 MHz. Should I not expect clock stretching to work?
Also, is the data sheet up to date regarding max clock rate? I see 25, 45, and 75 MHz in various datasheet versions and forum answers.
Thanks
