• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 336 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04828: How the SYNC impact sysref?

shen jie
Intellectual 255 points
Part Number: LMK04828

Hi，

I‘m very curious about

1. How the input SYNC impact SYSREF?

2. why the figure2 is different form figure1 about the flow direction of continue 5MHz SYSREF ?

As below figure1 shown, 5MHz SYSREF frequency is independent with SYNC event fully through SYSREF_MUX, that mean only one could be selected between continue 5MHz SYSREF and SYNC(Normal/re-clocked/pin pulse) as source into SYSREF distribution path directly. 

Thanks in advance

Figure1. continue 5MHz SYSREF is input into  SYSREF_MUX

Figure 2 continue 5MHz SYSREF is input into SYSREF distribution path directly, why 

  • 0
    TI__Genius 12560 points

    Hi,

    In LMK04828, SYNC and SYSREF signals share the same clocking path but with different settings. To know more on the each section settings, follow the section 9.3.1 in datasheet. 

    shen jie said:
    1. How the input SYNC impact SYSREF?

    Actually, the sync doesn't impact on SYSREF but it utilizes the same path for reset / synchronizing the device. Figure 13 shows the SYNC/SYSREF clocking path block diagram for details.

    shen jie said:
    2. why the figure2 is different form figure1 about the flow direction of continue 5MHz SYSREF ?

    During the SYNC event, SYSREF_MUX set to Normal_SYNC and uses the SYNC/SYSREF path for reset. At this time, SYSREF should be OFF. Whereas for SYSREF out, SYNC should stop and SYSREF_MUX set for Continuous or Pulsar mode based on requirement with the configured output frequency.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Intellectual 255 points

    Hi, 

    Thank for your response:)  Your response is very helpful for me to understand LMK04828B.

    Your meaning is SYNC and SYSREF couldn't take effect at the same time although they share the same path

    Since  SYNC and SYSREF are only switched by SYSREF MUX, I think it means only one could take effect at certain moment

    But SYNC_DISX and SYNC_DISSYSREF means they could happen at the same time:

    When SYNC_DISX =0, clock or sysref output could be impacted by SYNC event

    When SYNC_DISX =1, clock or sysref output couldn't be impacted by SYNC event

    So, first question is  How I understand the SYNC_DISX and SYNC_DISSYSREF?

    second question is how could i understand SYSREF_GBL_PD or what meaning of conditional low?

     Many thanks to you!!!

    Best regards!

    Jason

  • +1 in reply to shen jie
    TI__Genius 12560 points

    Hi Jason,

    That's correct. SYNC and SYSREF only one will be operating at a time. SYNC_DISX and SYNC_DISSYSREF bits low enable the sync to reset the dividers (DCLK and SYSREF dividers respectively) for synchronization. After SYNC event, make these bits to high and enable SYSREF path.

    With SYSREF_GBL_PD bit 1, it enables the each SYSREF outputs to operate in power down mode and can be set based on setting of SDCLKoutY_DIS_MODE.

    If SYSREF_GBL_PD bit is 0, SYSREF output doesn't affect with SDCLKoutY_DIS_MODE settings.

    For SYSREF_GBL_PD bit 1, each SYSREF output would be set as normal operation (0x00), SYSREF output active low --> 0V (0x01), SYSREF output to Vcm voltage (0x02) based on SDCLKoutY_DIS_MODE settings.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Intellectual 255 points

    Hi,

    I get your point, and very very appreciate your help：）

    Thank you very much!!!

    Best regards!

    Jason