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CDCE62005EVM: When the frequency shifts, it will be out of sync.

?? ??
Prodigy 10 points
Part Number: CDCE62005EVM
Other Parts Discussed in Thread: CDCM6208

I want to create a multiplying wave that changes following a reference signal with a fluctuating frequency.
I want to synchronize the reference signal at 1.7MHz and change it within the range of ± 2%.
As a result of testing using the evaluation module (CDCE62005EVM), synchronization was lost about 50Hz before.
Of course, Synchronize when set directly to the maximum and minimum frequencies.
The frequency change is slow enough.

I don't know the cause, so I'd like some advice.

------test date---------

Refarence Frequency :1.7MHz (1.666～1.734MHz)
Reference Divider :1/1
1.602-1.721 :locked
Outside it     :unlocked

Output Frequency :163.2MHz(159.936～166.464MHz)　:Ref*96
Output Divider :1/4

VCO Frequency: 1.9584GHz (1.919232～1.997568GHz)
Prescaler :1/3
Feedback Divider:1/384
VCO1 used

  • 0
    TI__Mastermind 18070 points

    Hello,

    When the frequency is changed by too much you'll have to recalibrate the VCO otherwise it'll lose lock. I think you are looking for a device which can do glitchless frequency increment/decrement over a pretty wide range. CDCM6208 should be it. The last 12 bits of FOD (FRACDIV[11:0]) can be changed on the fly.

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 10 points

    Dear. Hao

    Thank you for the suggestion.

    >When the frequency is changed by too much you'll have to recalibrate the VCO otherwise it'll lose lock.

    I found out about sub-band in another thread (e2e.ti.com/.../cdce62005-vco-calibration-word).
    Does it mean that the lock is released when the frequency goes out of the subband?
    Is the bandwidth of the subband listed in the data sheet etc.?


    >The last 12 bits of FOD (FRACDIV[11:0]) can be changed on the fly.

    Does this mean monitoring the frequency of the reference and changing the registers on the PC?
    That process doesn't meet my needs. When using it, I would like it to operate independently without being connected to a PC.
    Does this mean changing the registers on the PC with monitoring the frequency?
    That process doesn't meet my needs. When using it, I would like it to operate independently without PC.

    I will read the data sheet of CDCM6208.

    Best Regards,

    okada

  • 0 in reply to ?? ??
    TI__Mastermind 18070 points

    Hi Okada,

    Sorry I misunderstood your question. If the reference frequency is changing and the PLL configuration is fixed then there are two options: (1) you'll still have to manually recalibrate the VCO when frequency changes, (2) otherwise you'll need to set the PLL loop bandwidth to be very wide (as wide as possible). If it still doesn't work then you may need to find some clock and data recovery device because this is not how a clocking PLL is usually used. A clocking PLL is usually locked to a pretty stable reference (less than 100 ppm).

    Regards,
    Hao

  • 0 in reply to Hao Z
    Prodigy 10 points

    Dear. Hao

    Thank you again for your response.

    >then there are two options: (1) you'll still have to manually recalibrate the VCO when frequency changes, (2) otherwise you'll need to set the PLL loop bandwidth to be very wide (as wide as possible).

    Yes.
    Since my reference frequency changes continuously, method (1) cannot be used. Therefore, (2) was selected.
    I thought I could continuously change the frequency of the built-in VCO from minimum to maximum, but in reality it was not such a specification. I am very disappointed for that.
    (I think TI should write this in the datasheet.)

    By the way, what other ways can I achieve my original goal?
    I would appreciate it if you could teach me.

    Best Regards,

    okada

  • 0 in reply to ?? ??
    TI__Mastermind 18070 points

    Hi Okada,

    Normally there's a bank of capacitors to choose from for the LC VCO. As a result, you'll need VCO calibration when VCO frequency is changed in order to select the right settings. If increasing the PLL loop bandwidth still doesn't solve the problem then unfortunately I can't think of other solutions from the clocking portfolio. As mentioned before you may have to look for some CDR devices but I'm not very familiar with the details.

    Regards,
    Hao