LMK04826: Tracked CPout1 Holdover Mode

Hi JH,

Per section 9.3.7.2 of the datasheet, there are several ways to enter holdover:

• If LOS is enabled (LOS_EN=1, HOLDOVER_LOS_DET=1) and a loss of signal is detected on the active reference clock (CLKin1 in customer programming). This is not active in customer programming. Note that if the customer chooses to enable this mode, LOS_TIMEOUT should be set to the highest setting (22MHz) for the presumed 30.72MHz reference clock that seems to correspond to a valid VCO frequency. This condition would only trigger holdover if the reference clock did not generate an edge for >1/LOS_TIMEOUT seconds - in the 22MHz case, 50ns. A small ppm tilt on the reference clock frequency will not be enough to trigger LOS holdover.
• If lock-detect holdover is enabled (HOLDOVER_PLL1_DET=1) and the active reference clock goes beyond the required PPM for lock. This is not active in customer programming. Note that PLL1 with external VCXO will attempt to tune the VCXO voltage to a value that keeps PLL1 locked, so a fairly large ppm offset at the reference would be required to put the device in holdover for any extended duration. Depending on the loop bandwidth, phase detector frequency, and magnitude and slew rate of reference tilt, PLL1 may be able to respond to the change in frequency fast enough to not enter holdover at all; on the other hand, if the loop cannot respond quickly enough and lock detect is lost, the device will enter holdover and stay there due to the tracked CPout1 voltage, until the reference frequency returns to a value that closely matches the VCXO frequency when set to the tracked CPout1 voltage. There is also an edge case in holdover mode where the reference frequency matches the VCXO frequency, but the phase error between the reference and feedback paths is large enough that the digital lock detect cannot indicate a lock status, and it may take a very long time for the phase error to shrink enough that the digital lock detect circuit begins registering valid phase detector comparisons. In this case it may be useful to introduce a slight error to the VCXO frequency by reading back the DAC value, programming this value ±1 to MAN_DAC, and toggling MAN_DAC_EN.
• If Vtune monitoring is enabled (HOLDOVER_VTUNE_DET=1) and the Vtune voltage crosses below the threshold programmed by DAC_TRIP_LOW or above the threshold programmed by DAC_TRIP_HIGH. This can be used to restrict the tuning voltage range of the VCXO, and can effectively reduce the permissible ppm offset below the pull range of the VCXO. This is useful in cases where the reference may drift slowly, but the actual unlock range is much narrower than the pull range of the VCXO. While this is enabled on customer programming, the default values for DAC_TRIP_LOW and DAC_TRIP_HIGH are used, implying that the device will only enter holdover if the Vtune voltage at CPout1 is in the lower or upper 64th of the total voltage range (for 3.3V supply, <51.5mV or >3.2485V) - in other words, holdover will only enter if the reference frequency is completely outside of the tuning range of the VCXO. Since the DAC_TRIP values are quantized into 64ths of the CPout1 tuning voltage range, as long as the VCXO's frequency gain is known, it should be straightforward to calculate the DAC_TRIP values for a given PPM offset, and to produce a tilted reference beyond the limits of the DAC_TRIP thresholds.
• If HOLDOVER_FORCE=1, the device will be forced into holdover independent of other conditions. This is useful for testing behavior in holdover, but not for checking the transition conditions.

Regards,

Derek Payne