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LMK03318: IBIS model source output terminations

Larry Shaffer
Prodigy 240 points
Part Number: LMK03318
Other Parts Discussed in Thread: TMS320C6678,

Hello,

We are doing some Hyperlynx simulations for the LMK03318 output clocks driving the TMS320C6678 DSP. For the LMK03318 we are using it in Hard-mode with ROM Option 45 (LVPECL outputs). We see from the E2E questions that the DSP IBIS model did not include the termination resistors, so we added those. But we are uncertain as to if the IBIS model for the LMK03318 includes the source output terminations?

Please refer to page 46 of the LMK03318 datasheet for the reference to "No source termination is needed since the on-chip termination is automatically enabled when selecting AC-LVDS, AC-CML, or AC-LVPECL". Are these source terminations a default for the IBIS model, or do we need to make some settings or customization to the model?

The attached spreadsheet has 3 tabs for the 3 clock outputs we are using.

Regards,

Larry

C10509 AVAYA DAR 6 RESULTS 20-4-22.xlsx

  • 0
    TI__Mastermind 28550 points

    Hello Larry,

    For the AC-xxx formats, nothing special needs to be done for source terminations.  You should just be able to use as-is.

    I see you're waveforms leave something to be desired.  If you disconnect the TMS target and use just the 100 ohm termination, does that clean-up the waveform?

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 240 points

    Hi Timothy,

    Thanks for your help.

    We have re-run the Hyperlynx simulations with just the 50 ohm termination on each side at the DSP end as you suggested. The problem persisted with the AC-LVPECL and the other AC-models. We tried the DC models and they look good, but of course, we know that we need to use AC-PECL since we are in Hardmode with ROM Option 45. This option will provide the TMS320C6678 DSP with the 3 clocks that it needs directly. 

    The we ran AC and DC simulations with the series capacitors removed, just to see how they are affecting things, and the waveforms look much better. We have 0.1uF capacitors in the actual design as recommended by the TI documents, 0201-size capacitors. 

    Attached is a spreadsheet showing the Hyperlynx simulation circuits and the simulation results.

    Beside the waveform shapes, the most critical concern is the voltage levels that we have here. If you could offer guidance for that, I would appreciate it.  That is our biggest problem here. We see from the LMK03318 datasheet that the AC-LVPECL outputs can have a differential swing of up to 1.8V, since we are powering the LMK03318 outputs from a 1.8V supply. But the problem is that in the TMS320C6678 datasheet we see in the Absolute Maximum Ratings that for the LJCB inputs they must not go above 1.3V. 

    We see in TI document SCAA059C on the bottom of page 4 and the top of page 5:, "In the case where the differential LVPECL output is larger than what the CML receiver can tolerate, then Ra should be used to attenuate the LVPECL output such that it meets the input voltage required for the CML receiver." My question for you, Timothy, is what value of resistor should we use for Ra as shown in Figure 6 of SCAA059C? 

    Regards,

    Larry

    C10509_Avaya_DAR6_LVPECL_Tests_17-4-22.xlsx

  • 0 in reply to Larry Shaffer
    TI__Mastermind 28550 points

    Hi Larry,

    Larry Shaffer said:
    Beside the waveform shapes, the most critical concern is the voltage levels that we have here. If you could offer guidance for that, I would appreciate it.  That is our biggest problem here.

    For the AC coupled, I think you many need to use something like 100 pF or less for the waveforms to achieve some steady state.

    VOD for "AC-LVPECL" in LMK03318 datasheet is 500 mV to 1000 mV, which means the peak to peak differential swing would be 1000 mVpp to 2000 mVpp. 

    Larry Shaffer said:
    what value of resistor should we use for Ra as shown in Figure 6 of SCAA059C? 

    So the key thing to understanding AC-LVPECL is that it is not LVPECL.  It's more like high swing LVDS to my understanding.  I'm of the opinion it should be called something different like HSDS (we call other differential output swings in other products HSDS -- high swing differential signaling), because it is not emitter coupled logic in reality - anything showing LVPECL terminations with emitter resistors does not apply.  Of course in this case, you can simply omit the emitter resistors.  For Ra, if you want to limit the LMK03318 max VOD = 1000 mV to LVPECL VOD = 800 mV, I would set Ra = 12.5 ohms = (100 ohms diff term / (800 mV / 1000 mV) - 100 ohms term) / 2

    What is LJCB?  Ahh, low-jitter clock buffer.  I see the abs max on page 116 of the TMS320C6678 datasheet, the next page shows recommended operating conditions, but I don't see LJCB.  It seems there is some more info in this thread with good links:

    https://e2e.ti.com/support/clock-timing-group/clock-and-timing/f/clock-timing-forum/312730/clock-input-buffer-voltage-level-for-c6678

    73,
    Timothy

  • 0 in reply to Timothy T
    Prodigy 240 points

    Hi Timothy,

    Thank you for your help.

    Regards,

    Larry