LMK05028: Bit slip in ZDM

Hello Mita-san,

I think I have an answer for you, but also want to be sure I understand your question...

user4779049 said:

Q1. I suppose that D-PLL compares the phases between the reference input
      and an output clock directly feedback from the output port without any
      feedback divider in ZDM.
     Is my understanding correct?

When not using ZDM, the feedback path follows the green path back to the PR divider (prescaler divider) and then the FB divider (feedback divider).  This frequency is compared to the IN0 frequency after R divider.

Note from page 43, the various PLL equations are given.

When ZDM is used, then instead of using the output of the post divider, the output of a clock output is fed back to the TDC.

  * It seems from this picture the feedback divider is bypass, but I am not 100% sure on that and will need to check more.

  * But in either case, I don't have concern about the slip of a cycle when the device is locked.  At some point I suppose jitter could be so bad that the signal isn't able to be tracked in which case there could be some phase change.  However you can see from our testing the LMK05028 meets the G.8262 jitter tolerance tests.  See this application note.

user4779049 said:

Q2. If my understanding correct, I have one more question.
      I concern that, under a situation,
       (a). the frequency ratio between reference input and output clock is substantially
             large (say 1 vs. 1,000 or more) and
      (b). the jitter of the reference input is equal or larger than the output clock period,

Once locked, there would be no issue with the input phase and output phase staying locked.  Even with a large difference between input and output frequency.  If needed for a very noisy signal, you could increase the loop bandwidth of the DPLL to allow it to track faster.

However please see the rules for ZDM in this application note on page 7.

As for the large jitter on input signal... a several picosecond RMS jitter is quite a lot.  Lets assume a very large jitter of 100 ps RMS.    Period of 100 ps is 10 GHz!  So I don't expect you would be anywhere near this (b) concern.

Let me know if this answers your question.

73,
Timothy

Hello Mita-san,

So two items,

(1) with 6 ns output clock (166 + 2/3 MHz), the clock must be divided down to a lower frequency at TDC to allow it to lock.  Max TDC frequency is 26 MHz.  This means the period of concern for bit-slip would be 38.46 ns or more.
  * I need to confirm if it is possible to use the feedback frequency with the LMK05028 (i.e. it can divide down the 166+2/3 MHz in ZDM) or if you need to use another clock at a lower frequency (like 16 + 2/3 MHz).

(2) I think you need to consider the RMS jitter value for your bit-slip concern.  The relationship between peak to peak jitter and RMS jitter is a statistical one.  Depending on how long you sampled to measure your peak to peak (the longer you sample, the bigger your p2p measurement will become).  You could divide the p2p by the scaling factor to determine what the RMS jitter is, but it would be better to directly measure the RMS jitter.  If I assume one of the smaller multipliers, 7.4, even 10 ns / 7.4 = 1.35 ns rms which is less than the 6 ns, so I don't see any bit slip issue.  Even if there was an input edge greater than 6 ns, it would be much less likely than the majority of input clock edges meaning I expect the DPLL would filter your input so the output is well behaved without bit-slips but have not tested it myself as I don't have such a clock.

73,
Timothy