• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 740 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2820: Phase Synchronization of Multiple LMX2820's

Tony Rohlev1
Prodigy 40 points
Part Number: LMX2820
Other Parts Discussed in Thread: LMX2595, LMK04832

Dear TI LMX Team,

Assume there are several, say 8, LMX2820's operating at the same output frequency that require a Category 3 phase synchronization after a Reset, frequency re-programming, power-up, or some other output phase disruptive event. Also assume that the circuit is carefully laid out in such a way that path lengths from the common 100 MHz OCXO reference source to the various OSCIN pins are within a small fraction of a nanosecond. Likewise, the path lengths from the SYNC pulse source to the various PSYNC pins are also nearly identical. Lastly, lets also assume the SYNC pulse is locked to the OCXO reference so that it will always arrive at the LMX2820's at the same delay relative to rising edge on the OSCIN pin. This constant delay however is unknown.

The datasheet specifies that the minimum setup time between the PSYNC edge and the OSCIN rising edge is 2.5 ns - meaning the PSYNC pulse must be present and stable for at least 2.5 ns before the rising edge on the OSCIN pin. The datasheet also specifies that the hold time (pulse length) of the PSYNC pulse must be at least 2 ns - which we assume is not a problem, it will be far longer.

My question is in two parts - for the first part I'm afraid I know the answer, for the second part I'm afraid of the actual answer.

First: Is there are way the LMX2820 can indicate, through changing a bit in a register, that it has received a valid PSYNC event and initiated (or completed) a phase synchronization sequence? For the LMX2595 the answer from Dean was that no such bit exists and the only way to confirm that the phase sync event was successful was to look at the phases of the various LMX outputs with a scope - a decidedly unattractive and expensive proposition for say an 18 GHz output. I imagine things haven't changed for the LMX2820 - but it would be great if I'm wrong!

Second: If the PSYNC edge happens to occur inside the 2.5 ns setup zone (a 1 in 4 chance for a 100 MHz reference signal) - so that it violates the setup time requirement - can it be assumed that phase synchronization will NOT occur in ANY of the devices, or (I fear more likely) will the case be that some devices might initiate a the phase alignment procedure on that rising edge while the rest initiate it on the next rising edge and thus the outputs will not be aligned?

If the answer to the second part is that if the setup time is violated no phase synchronization will be initiated under any circumstances, then there is a simple solution (outlined in the LMX2595 blog) on how to guarantee a new PSYNC pulse can be made that absolutely obeys the setup time and imitates a valid phase sync even in all the devices on the same OSCIN edge.

If the answer to the second part is that if the setup time is violated it might initiate a phase sync even is SOME, but not all, of the devices .... then we're back to our 20 GHz scope (with 20 GHz probes)  and the pain of it all!

Request: In your next iteration of this great PLL can you please add a bit that says a phase sync even occurred?  

Thank you and all the best,

Tony

  • 0
    TI__Genius 12560 points

    Hi Tony,

    Tony Rohlev1 said:
    First: Is there are way the LMX2820 can indicate, through changing a bit in a register, that it has received a valid PSYNC event and initiated (or completed) a phase synchronization sequence? For the LMX2595 the answer from Dean was that no such bit exists and the only way to confirm that the phase sync event was successful was to look at the phases of the various LMX outputs with a scope - a decidedly unattractive and expensive proposition for say an 18 GHz output. I imagine things haven't changed for the LMX2820 - but it would be great if I'm wrong!

    I am afraid to say that your understanding is correct. The LMX2820 doesn't have any bit to indicate the valid PSYNC event as each device can have their own valid event, if there is an skew (delay) on the OSCin input of the multiple devices. The SYNC event occurs with respect to the raising edge of the OSCin of the device and if PSYNC input maintain the setup and hold time requirement, multiple LMXs output would be aligned or have deterministic phase.

    The device can have a bit, which indicates that the SYNC event occurred or not. But it will not say SYNC between multiple devices. It is useful for debug purpose.

    Tony Rohlev1 said:
    Second: If the PSYNC edge happens to occur inside the 2.5 ns setup zone (a 1 in 4 chance for a 100 MHz reference signal) - so that it violates the setup time requirement - can it be assumed that phase synchronization will NOT occur in ANY of the devices, or (I fear more likely) will the case be that some devices might initiate a the phase alignment procedure on that rising edge while the rest initiate it on the next rising edge and thus the outputs will not be aligned?

    If the PSYNC violates the setup and hold time requirements, the sync will not be reliable and any of the device can take the coming raising edge or next raising edge of the OSCin for synchronization. Hence, as mentioned in datasheet, SYNC timing is critical in category 3.

    As an example of 100MHz OSCin frequency, the valid window for the PSYNC event would be 5.5 ns (10 - 2.5 (setup time) - 2 (hold time) = 5.5 ns) and all SYNC should be in this time.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Prodigy 40 points

    Hi Ajeet,

    Thank you for your answer.

    Ok, so as I feared if the setup and hold times are violated (the setup being the tricky one) then there will be an ambiguity as to on which OSCin edge the various devices initiated their synchronization sequence and then all bets are off as to the final phase results.

    Good to know.

    As to a bit indicating that a synchronization sequence has occurred in a device it will be useful, but only if the entire period of the SYNC pulse is less than the period of the OSCin clock (in this case 10 ns). If that can be done (and that itself is not trivial) then the user sends a single SYNC pulse and then queries each device to see if they saw it. If they all saw it then chances are very good they are now all phase aligned. If not, send another pulse and do it all again. Still, a 10 ns pulse is not trivial to make.

    So maybe the best solution is to have a way of creating a SYNC edge (with the entire SYNC pulse being as long as one likes), locked to the OSCin clock with a flip-flop and then using a normal scope to check the relation between the SYNC edge and the OSCin edge at the device to verify that the setup and hold times are obeyed. If they aren't, no problem, just use the inverse clock signal to lock the SYNC to and it WILL obey the setup and hold times. Then never change the circuit and initiate a SYNC event at will and you are guaranteed all the devices will be phase aligned .... but still check it with the GHz scope on the output once in a while to make sure.

    Does this sound OK to you?

    All the best,

    Tony

  • +1 in reply to Tony Rohlev1
    TI__Genius 12560 points

    Hi Tony,

    Tony Rohlev1 said:
    As to a bit indicating that a synchronization sequence has occurred in a device it will be useful, but only if the entire period of the SYNC pulse is less than the period of the OSCin clock (in this case 10 ns). If that can be done (and that itself is not trivial) then the user sends a single SYNC pulse and then queries each device to see if they saw it. If they all saw it then chances are very good they are now all phase aligned. If not, send another pulse and do it all again. Still, a 10 ns pulse is not trivial to make.

    SYNC input/event indication bit only tells that the external SYNC input came but not tell at what instant it is. If SYNC single pulse is less than OSCin cycle, yes SYNC bit will indicate that SYNC event occur if it meet the setup and hold time. 

    Tony Rohlev1 said:
    So maybe the best solution is to have a way of creating a SYNC edge (with the entire SYNC pulse being as long as one likes), locked to the OSCin clock with a flip-flop and then using a normal scope to check the relation between the SYNC edge and the OSCin edge at the device to verify that the setup and hold times are obeyed. If they aren't, no problem, just use the inverse clock signal to lock the SYNC to and it WILL obey the setup and hold times. Then never change the circuit and initiate a SYNC event at will and you are guaranteed all the devices will be phase aligned .... but still check it with the GHz scope on the output once in a while to make sure.

    That's true to have a synchronous SYNC input. SYNC input should always be synced / locked with the OSCin and can be get it as you mentioned through flip flop. But it would need an accurate measurement at the device pins for alignment between the OSCin and SYNC inputs. For a SYNC alignment validation, it would not need an high oscilloscope for SYNCed output. With the SYCN input, one can have low end scope and can see use the LMX2820 divided output, which will validate SYNC input and keep the same for high frequency out.

    Also can have delay adjustment in SYNC input for avoid the setup and hold timing requirements.

    For an example, TIDA-010230 reference design uses the LMK04832 to provide the SYNC inputs (along with other clocks) to multiple LMX2820 and which has an option for SYNC delay.

    Thanks!

    Regards,

    Ajeet Pal