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LMX2594: EVM evaluation : Phase noise with LMK61PD0A2 clock input

Yusuke Mukuno
Expert 7395 points
Part Number: LMX2594
Other Parts Discussed in Thread: LMK61PD0A2

Hi Expert,

My customer is evaluating LMX2594EVM.


When They checked the Phase Noise of 8GHz output when the Ref Clock input to the PLL was used with the LMK61PD0A2 set to 100MHz,

The data sheet Figure 53 shows -110dBc / Hz at 10kHz, but the actual measurement is -105dBc / Hz, which is about 5dB worse.

Is it possible to obtain performance of about -110dBc / Hz even when the Ref Clock is LMK61PD0A2?
Ref Clock is a modified EVM and is input differentially.
Loop filters are the default values.

evaluation results

TICS pro setting

Thanks

Muk

  • 0
    TI__Guru* 92090 points

    Hi Mukuno-san,

    To get -110dBc/Hz at 10kHz offset, we need a very good reference clock. Datasheet data was taken with Wenzel clock, its phase noise at 10kHz offset is -115.6dBc/Hz. With LMK61PD0A2, the phase noise at this offset is -147dBc/Hz. There is no way to tweak the loop filter to get the performance as if using the Wenzel clock.

  • 0 in reply to Noel Fung
    TI__Expert 7395 points

    Hi Noel-san,

    Thank you for your supporting.

    Customer have additional questions about PFD_DLY_SEL setting.

    Customer refer the datasheet table2. 

      The recommended value in the datasheet is "5" at Fout  7.6GHz.

      The recommended value in the datasheet is "5" at Fout  7.7GHz.

    However, if they modify this value at 7.6GHz and 7.7GHz as below,  they can get better performance of phase noise than recommended value.

      The modified value is "6" at Fout  7.6GHz.

      The modified value is "7" at Fout  7.7GHz.

    Do you have any consern about this modification?

    Thanks

    Muk

  • 0 in reply to Yusuke Mukuno
    TI__Guru* 92090 points

    Hi Mukuno-san,

    This is not surprising, this register has +/- 1 for use to adjust. Sometime we can get a bit better performance with a little different value from datasheet's recommendation.