• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 21 subscribers
  • Views 907 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Looking for PLL/ clock clean-up solution with ultra low phase noise & low wander capabilities

Freddy Severino
Prodigy 20 points
Other Parts Discussed in Thread: LMK5B33216, LMK05318B

I am looking for PLL/ clock clean-up solution with ultra low phase noise & low wander capabilities. Need to have the best phase noise performance for close-in noise from (1 Hz up to 1 MHz). Need the device to come-up in freeRunning mode at power up and then to allow it to lock to ext-ref 100 MHz clock when clock is present.  We also need the option of 0-delay with output from final divider to guarantee zero phase with respect to input clock. We have a ultra low noise and very low wander 100 MHz clock with (1 Hz to 10 KHz) integrated rms phase jitter of about 100 fsec or less. We need to try to keep as much of the good phase noise performance below from (1 Hz to 10 KHz) and try to improve (lean up) our clock phase noise above 10 KHz. We need to generate (62.5 MHz, 100 MHz, 125 MHz, 156.25 MHz, 200 MHz and 400 MHz). 

   I just order LMK5B33216 Eval Board to start playing with it. Not sure if this device has the potential for doing what we need.  Any advice is appreciated, very happy to chat with someone.

--Freddy

  • 0
    TI__Mastermind 28550 points



    Hello Freddy,

    I think the LMK5B33216 could be a great solution for you.

    The LMK5B33216 requires an XO/TCXO/OCXO input to operate.  If you always knew you would have your very good 100 MHz reference, you could simply use that as your XO input and then do an integer PLL lock to APLL3 (BAW PLL @ 2500 MHz) for the best possible performance.  (1) great high frequency high quality reference (2) integer mode.
      - Now you wouldn't be able to generate 200 MHz or 400 MHz from APLL3, but APLL2 could be programmed to generate 200 MHz and 400 MHz.   Do you have any phase requirements between 200 MHz/400 MHz and the other clocks?
      - Note LMK05318B could also be a solution if you don't need as many outputs.
      - This example case doesn't actually use the DPLL - and maybe you want these features (sounds like you may - if starting without your 100 MHz ref and still needing output clocks).

    So to get start up with output clocks but your very good 100 MHz reference is not available, then then you must select an XO frequency which does not have an integer relationship to the VCO frequencies your application will use, for example 2500 MHz (meaning 100 MHz is a no-go).  Our eval board uses 48 MHz.
      - At power up the EEPROM can be programmed to use the 48 MHz (or other frequency) to lock APLLx to and then generate all output frequencies.
      - When your 100 MHz reference comes up on an INx input.  The DPLL will validate it and lock to it by servoing the APLLx numerator to keep the VCO lock to the INx reference.
      - If the reference goes away, the DPLL will enter holdover and continue operating with the long term stability of your XO/TCXO/OCXO on XO input port.

    Below DPLL loop bandwidth your clock noise to INx + DPLL noise will dominate, between DPLL loop bandwidth and APLL loop bandwidth the XO noise + APLL noise will dominate.  Above APLL loop bandwidth the VCO (or BAW) will dominate.
      - The BAW (VCO3) has very good performance above 10 kHz vs. XO and can be be used as a cascaded reference (instead of XO input port) for APLL1 or APLL2.  Because you could run the APLL1/2 PDF higher from the cascaded BAW, this will give better performance above 10 kHz in my experience.  However if sub-10 kHz is the most important, you'll probably be better off using the XO reference for the APLL1/2.

    So if your INx is very good performance, you may consider a wide loop bandwidth, but be sure to stay at 10x below the APLL LBW.

    Hope this helps.

    73,
    Timothy