We are using the CDCE949 with an external 20 MHz crystal, so the CDCE949 is used as crystal buffer with cascaded PLLs to provide the required clock (e.g. 25 MHz, 33 MHz etc). According datasheet no maximum time for start-up time is specified. According section 10.2.2.3 and figure 18 a typical startup time of 250us + 10us PLL lock time is specified if a 27 MHz crystal with 8 pF load is assumed. What can we expect as maximum start-up time? As start-up time I would define the delay in giving a programmed output clock after the power rails are settled. If we are well below e.g. 1 - 2 ms everything is fine but the information is missing. Thanks in advance.
Best regards,
Andreas N.
