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LMK04828: How to syncronize multiple boards

Part Number: LMK04828

Hello,

I am checking some documnets of TI about multi-lmk sync, but still being confused. Please checking my concept.

There are a master board and several slave boards on system. Master board sends REFCLK and SYNC signal(not a SYSREF) to slaves via fan out buffer.

Each slave board has two lmk04828s to provide devclk and sysref to adc, dac and fpga.

1> connection of REFCLK and SYNC to 1st and 2nd LMK on slave boards.

REFCLK and SYNC are connected to OSCin and CLKin0 of 1st-LMK respectively, and DCLKout12 and SDCLKout13 of 1st-LMK are connected to OSCin and CLKin0 of 2nd-LMK respectively.

Is it possible to set 1st-LMK as like SDCLKout1~SDCLKout11 as a SYSREF and SDCLKout13 as a SYNC(or bypassing CLKin0) 

2> connection to SYSREF_REQ for implementing subclass 1

All sync_in and sync_out signals from/to adc and dac are ANDing inside fpga and the result of ANDing is connected to SYSREF_REQ pin pf 1st-LMK and 2nd-LMK.

 3> how to assert SYSREF_REQ pin simultanously among the slave boards?

For simultaneous operation of ADC and DAC on slave boards should operate simultaneously. does a trigger signal need to be connected to SYSREF_REQ pin on each slave board? 

  • Hi,

    From the description above, your operating architecture uses Tree and daisy chain configuration. Where Primary LMK (called Master) uses as host to provide the REF clock and SYNC signals to 1st secondary LMK (called slave), it is called tree configuration. later 1st secondary LMK provide REF clock and SYBC signals to 2nd secondary LMK (called slave).

    To get more details of these configurations, I would suggest to go over the TIDA-01023 and TIDA-01024 TI reference designs. There is an difference as these are using in distribution mode and should be valid for PLL mode also.

    Regarding to your queries:

    1. Yes, 1st secondary LMK SDCLKout13 can be used as SYNC out (which is nothing but SYSREFout but using in pulse mode) for 2nd secondary LMK. After sync operation, 1st LMK SDCLKout1-11 can be used as SYSREF for data converters

    2. There can be issue, when the SYSREF_REQ generates from FPGA after ANDing in single secondary LMK board . How the other secondary board SYSREF will be aligned each other, if individual FPGA providing the SYSREF_REQ.

    3. To have simultaneously SYSREF out from each secondary board, there can be option to provide the SYSREF_REQ signal from primary LMK, which can get the commands from host FPG or ANDing signal from each FPGA in secondary LMK board.

    Thanks!

    Regards,

    Ajeet Pal