Hello,
I am checking some documnets of TI about multi-lmk sync, but still being confused. Please checking my concept.
There are a master board and several slave boards on system. Master board sends REFCLK and SYNC signal(not a SYSREF) to slaves via fan out buffer.
Each slave board has two lmk04828s to provide devclk and sysref to adc, dac and fpga.
1> connection of REFCLK and SYNC to 1st and 2nd LMK on slave boards.
REFCLK and SYNC are connected to OSCin and CLKin0 of 1st-LMK respectively, and DCLKout12 and SDCLKout13 of 1st-LMK are connected to OSCin and CLKin0 of 2nd-LMK respectively.
Is it possible to set 1st-LMK as like SDCLKout1~SDCLKout11 as a SYSREF and SDCLKout13 as a SYNC(or bypassing CLKin0)
2> connection to SYSREF_REQ for implementing subclass 1
All sync_in and sync_out signals from/to adc and dac are ANDing inside fpga and the result of ANDing is connected to SYSREF_REQ pin pf 1st-LMK and 2nd-LMK.
3> how to assert SYSREF_REQ pin simultanously among the slave boards?
For simultaneous operation of ADC and DAC on slave boards should operate simultaneously. does a trigger signal need to be connected to SYSREF_REQ pin on each slave board?