I am using LMK04828 on a board of my own design to generate a 3GHz clock from a 10MHz reference. I have this working using cascaded PLLs, but I am having trouble changing the LMK04828 to use zero-delay mode. When I use the FB_MUX to feed 3GHz from DClk8 to PLL1 phase detector, PLL1 always reports unlock. On this board, I have used a different software variant to implement a 1GHz clock using zero-delay mode.
The differences between the working 1GHz ZDM solution and the 3GHz ZDM solution prompt the following questions:
- Is there a frequency limit when using the FB_MUX with DClk8? If so, does the same limit apply to DClk6?
- For the 1GHz clock, the DCLKout8_MUX is set to 0 (divider only). For the 3GHz clock, the DCLKout8_MUX is set to 2 (bypass). Does the divider bypass also bypass the path to the FB_MUX?
- Is there an errata for the PLL1_N upper bits register? For the 1GHz ZDM, PLL1_N is 100 = 0x64 and fits all in the lower bits register. For the 3GHz ZDM, PLL1_N is 300 = 0x12c and thus requires the upper bits register too.
