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LMK04828: SPURIOUS FREQUENCY FROM LMK

Part Number: LMK04828

Hi Derek,

we are using LMK04828 chip on our custom board and generating 256MHz clock and 4MHz SYSREF,we are seeing 25KHz spur on the dac output.
i would like to present my prob in two cases

CASE1 :
we have an eval board which is using LMK chip and DAC with CLKIN0 =10MHz and external VCxO as 160MHz,generating 256MHz clock and
4MHz SYSREF. we are generating DAC output from the board which is very clean and without any spurs. i hav attached the configuration file of it.

CASE2 :
on our custom board with LMK04828 chip and generating 256MHz clock and 4MHz SYSREF,we found two spurs at 25KHz apart from centre
we feel it is generated from the combination of both VCO(2560MH

eval_board_configuration.txt
R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01006A
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x010670
R263	0x010755
R264	0x01086A
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F11
R272	0x01106A
R273	0x011155
R274	0x011255
R275	0x011301
R276	0x011422
R277	0x011500
R278	0x011670
R279	0x011733
R280	0x01186A
R281	0x011955
R282	0x011A55
R283	0x011B01
R284	0x011C22
R285	0x011D00
R286	0x011E72
R287	0x011F01
R288	0x012074
R289	0x012155
R290	0x012255
R291	0x012301
R292	0x012422
R293	0x012500
R294	0x012678
R295	0x012733
R296	0x01286A
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F00
R304	0x01306A
R305	0x013155
R306	0x013255
R307	0x013301
R308	0x013422
R309	0x013500
R310	0x013673
R311	0x013700
R312	0x013800
R313	0x013903
R314	0x013A02
R315	0x013B80
R316	0x013C00
R317	0x013D01
R318	0x013E03
R319	0x013F02
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014331
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01471A
R328	0x014806
R329	0x014946
R330	0x014A06
R331	0x014B06
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015013
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015401
R341	0x015500
R342	0x015601
R343	0x015703
R344	0x0158C0
R345	0x015900
R346	0x015A10
R347	0x015BDA
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F3E
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x0165A0
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016808
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E1B
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
VCO2560MHz_configuration.txt
R0 (INIT)	0x000090
R0	0x000004
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01000A
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x010670
R263	0x010755
R264	0x01086A
R265	0x010955
R266	0x010A55
R267	0x010BB1
R268	0x010C22
R269	0x010D00
R270	0x010E70
R271	0x010F11
R272	0x01106A
R273	0x011155
R274	0x011255
R275	0x0113B1
R276	0x011422
R277	0x011500
R278	0x011670
R279	0x011733
R280	0x01186A
R281	0x011955
R282	0x011A55
R283	0x011BB1
R284	0x011C22
R285	0x011D00
R286	0x011E71
R287	0x011F03
R288	0x012072
R289	0x012155
R290	0x012255
R291	0x0123B1
R292	0x012422
R293	0x012500
R294	0x012678
R295	0x012755
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013016
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013700
R312	0x013805
R313	0x013903
R314	0x013A02
R315	0x013B80
R316	0x013C00
R317	0x013D0E
R318	0x013E03
R319	0x013F05
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014321
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01470A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x01540A
R341	0x015500
R342	0x0156C5
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A64
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016105
R354	0x016245
R355	0x016300
R356	0x016400
R357	0x01650C
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016820
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
VCO3072MHz_configuration.txt
R0 (INIT)	0x000090
R0	0x000004
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x01000C
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x010670
R263	0x010755
R264	0x01086C
R265	0x010955
R266	0x010A55
R267	0x010BB1
R268	0x010C22
R269	0x010D00
R270	0x010E70
R271	0x010F11
R272	0x01106C
R273	0x011155
R274	0x011255
R275	0x0113B1
R276	0x011422
R277	0x011500
R278	0x011670
R279	0x011733
R280	0x01186C
R281	0x011955
R282	0x011A55
R283	0x011BB1
R284	0x011C22
R285	0x011D00
R286	0x011E71
R287	0x011F03
R288	0x012072
R289	0x012155
R290	0x012255
R291	0x0123B1
R292	0x012422
R293	0x012500
R294	0x012678
R295	0x012755
R296	0x012808
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C02
R301	0x012D00
R302	0x012EF9
R303	0x012F00
R304	0x013016
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013402
R309	0x013500
R310	0x0136F1
R311	0x013700
R312	0x013825
R313	0x013903
R314	0x013A03
R315	0x013B00
R316	0x013C00
R317	0x013D0E
R318	0x013E03
R319	0x013F04
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014321
R324	0x0144FF
R325	0x01457F
R326	0x014618
R327	0x01470A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x01540A
R341	0x015500
R342	0x0156C5
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A64
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016119
R354	0x016245
R355	0x016300
R356	0x016401
R357	0x016580
R369	0x0171AA
R370	0x017202
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x0168C0
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R371	0x017300
R386	0x018200
R387	0x018300
R388	0x018400
R389	0x018500
R392	0x018800
R393	0x018900
R394	0x018A00
R395	0x018B00
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53
z) and External VCXo(100MHz) used in the design because

1. we changed the VCO to 3072 we are not seeing the spur at 25KHz but since the VCO frequency which was selected is at the border of VCO range,we are getting other freq spurs and noise floor also getting increased.

2. we tried to change the external VCxo of 100MHz to 160MHz but in single loop PLL2 mode we still find the 25Khz spurious.

i have attached the configuration file for VCO of 2560MHz and VCO of 3072MHz.


is there any way to reduce the level of these spurs?


Thank You

  • Hi,

    I believe the captured data are not for 256MHz output frequency (300MHz) and it may have different configuration file and showing 25kHz offset spurs.

    From the provided config file for 100MHz VCXO and 256MHz output, you are involving PLL2_R divider to reduce the phase detector frequency for required VCO frequency, which is responsible to generate the spurs.

    To avoid these spurs, change the VCXO (external frequency) to 160MHz and remove/reduced the PLL2_R divider and see the performance.

    2. we tried to change the external VCxo of 100MHz to 160MHz but in single loop PLL2 mode we still find the 25Khz spurious.

    I am not sure, if you have reduced/removed the PLL2_R divider and still getting the spurs at 25kHz.

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Ajeet,

    Thanks for early reply ,

    1.The output frequency was 300MHz , i was mentioning about the clock used from the LMK are 256Mhz and 4Mhz as  sysref.

    2.My configuration for external VCXo of 160Mhz is same as above attached EVal board configuration file, the only change is i hav changed the external 

       OSCin to independent and turned off PLL1 .i am attaching my configuration for VCXo of 160Mhz for reference.

    3.i dint understood how can we remove PLL2_R divider .in my case it is 1 for 160Mhz oscin

    single_loop_160Mhz_oscin.txt
    R0 (INIT)	0x000090
    R0	0x000010
    R2	0x000200
    R3	0x000306
    R4	0x0004D0
    R5	0x00055B
    R6	0x000600
    R12	0x000C51
    R13	0x000D04
    R256	0x01006A
    R257	0x010155
    R258	0x010255
    R259	0x010301
    R260	0x010422
    R261	0x010500
    R262	0x010670
    R263	0x010755
    R264	0x01086A
    R265	0x010955
    R266	0x010A55
    R267	0x010B00
    R268	0x010C22
    R269	0x010D00
    R270	0x010EF0
    R271	0x010F11
    R272	0x01106A
    R273	0x011155
    R274	0x011255
    R275	0x011301
    R276	0x011422
    R277	0x011500
    R278	0x011670
    R279	0x011733
    R280	0x01186A
    R281	0x011955
    R282	0x011A55
    R283	0x011B01
    R284	0x011C22
    R285	0x011D00
    R286	0x011E72
    R287	0x011F01
    R288	0x012074
    R289	0x012155
    R290	0x012255
    R291	0x012301
    R292	0x012422
    R293	0x012500
    R294	0x012678
    R295	0x012733
    R296	0x01286A
    R297	0x012955
    R298	0x012A55
    R299	0x012B00
    R300	0x012C22
    R301	0x012D00
    R302	0x012EF0
    R303	0x012F00
    R304	0x01306A
    R305	0x013155
    R306	0x013255
    R307	0x013301
    R308	0x013422
    R309	0x013500
    R310	0x013673
    R311	0x013700
    R312	0x013800
    R313	0x013903
    R314	0x013A02
    R315	0x013B80
    R316	0x013C00
    R317	0x013D01
    R318	0x013E03
    R319	0x013F02
    R320	0x014089
    R321	0x014100
    R322	0x014200
    R323	0x014331
    R324	0x0144FF
    R325	0x01457F
    R326	0x014618
    R327	0x01471A
    R328	0x014806
    R329	0x014946
    R330	0x014A06
    R331	0x014B06
    R332	0x014C00
    R333	0x014D00
    R334	0x014EC0
    R335	0x014F7F
    R336	0x015013
    R337	0x015102
    R338	0x015200
    R339	0x015300
    R340	0x015401
    R341	0x015500
    R342	0x015601
    R343	0x015703
    R344	0x0158C0
    R345	0x015900
    R346	0x015A10
    R347	0x015BDA
    R348	0x015C20
    R349	0x015D00
    R350	0x015E00
    R351	0x015F3E
    R352	0x016000
    R353	0x016101
    R354	0x016244
    R355	0x016300
    R356	0x016400
    R357	0x0165A0
    R369	0x0171AA
    R370	0x017202
    R380	0x017C15
    R381	0x017D33
    R358	0x016600
    R359	0x016700
    R360	0x016808
    R361	0x016959
    R362	0x016A20
    R363	0x016B00
    R364	0x016C00
    R365	0x016D00
    R366	0x016E1B
    R371	0x017300
    R386	0x018200
    R387	0x018300
    R388	0x018400
    R389	0x018500
    R392	0x018800
    R393	0x018900
    R394	0x018A00
    R395	0x018B00
    R8189	0x1FFD00
    R8190	0x1FFE00
    R8191	0x1FFF53
    

  • Hi

    hope you resolve my issues,

    i was trying to debug the issue of this spur. i hav probed the DCLOCK  out of the LMK04828 and i found out that the spur was coming from the LMK it self.

    Even i hav tryed to change the VCo freq to 3000Mhz and still i could find the spur

    attached are the screenshoot .

  • Hi,

    Below are the captures of 256MHz output from LMK04828 with your above used config file with 160MHz VCXO.

    There are no spurs at 25kHz offset.

    From your results, I would be having few observations:

    1. Why the fundamental (256MHz) have less output power (< -10dBm)? There can be some setup issue. check the RF cable, etc..

    2. 25kHz is consistence. It may be from source. Can you replace the 160MHz/100MHz source and see the performance.

    Thanks!

    Regards,
    Ajeet Pal 

  • Hi Ajit

    I am working along with Manish

    Could you provide us with the captures for 256MHz CLK OUT using 100MHZ Eternal VCXO, 10MHZ Reference clock ? 

    Thanks & Regards

  • Hi,

    TI doesn't have the LMK04828EVM with 100MHz VCXO on board, hence I could provide the test data with external input from Sig gen at OSCin input and operate in single PLL mode.

    As mentioned above, while introducing PLL2_R divider in path, it added the spur and to remove the spur, change the input (VCXO) to 160MHz.

    With 100MHz VCXO/external input and having 256MHz output, you need to be incorporate the PLL2_R divider, which added spur, shown below.

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Ajeet

    I have few queries

    1. In the spur free image which you have sent for  256MHz with 160VCXO , which configuration of LMK are you using. single loop or dual loop??

    2.In the above image 256MHz with 100VCXO , the spurs is at 163KHz, how it is related to any of the clock which are generated and used in our config file?

    3. we have already tried with VCO of 2500MHz [PLL2 R Divider is 1] and found the spur at 60KHz

    Attached are the configuration file and the clock output

    We need to know the reason for the spur and also the relation of this spur frequency wrt any of the LMK clocks or VCXO or VCO

  • Hi Shekhar,

    1. The measurement with 160MHz reference external from sig gen and used in single PLL (PLL2 mode) only.

    2. I'll get back to you on this.

    3. As mentioned above, if you go with PLL2_R divider value 1, there is no spurs. I'll check this configuration in my setup and will update you.

    Thanks!

    Regards,

    Ajeet Pal

  • Hi Shekhar,

    As already mentioned over email, the spurs at 163.8kHz in LMK04828EVM generated through on board unused 122.88MHz VCXO. After powering down the VCXO, the spurs goes down and sees very clean output.

    OSCin – 100MHz, PFD – 40MHz, VCO – 2560M; Fout – 256MHz

    Thanks!

    Regards,

    Ajeet Pal