We are trying to use LMK04832 Dynamic Digital Delay.
The example in data sheet is used as reference, but I would like to check following.
(In datasheet p34 :8.3.4.3 Single and Multiple Dynamic Digital Delay Example )
Assuming the device already has the following initial configurations:
•VCO frequency: 2949.12 MHz
•CLKout0 = 368.64 MHz, DCLK0_1_DIV = 8
•CLKout2 = 368.64 MHz, DCLK2_3_DIV = 8
The following steps illustrate the example above:
1. Set DCLK2_3_DDLY = 4. First part of delay for CLKout2
Why should DCLK2_3_DDLY be set to 4?
We use 0-Delay mode, is it correct to understand that the CLKout used for feedback cannot be delayed?
Regards,
Sato
