How to configure the 0-delay mode of a single PLL MODE?
Single PLL mode configured according to datasheet。
The 0-delay mode in the data sheet is based on the Dual PLL mode
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
How to configure the 0-delay mode of a single PLL MODE?
Single PLL mode configured according to datasheet。
The 0-delay mode in the data sheet is based on the Dual PLL mode
Hi,
To have single PLL 0-delay mode configuration, you can follow the zero delay dual PLL section (9.4.2 Zero-Delay Dual PLL) and disable the PLL1. It is same as 0-delay single PLL configuration. Here is the app note on multi-clock synchronization shows the rules for 0-delay mode FYR.
Thanks!
Regards,
Ajeet Pal