Hi TI,
We're using CDCE6214-Q1 as our PLL for clocking FPGA board.
The PLL can be successfully configured via both FPGA host IIC and TICS Pro.
But the PLL could not be configured anymore after programming again via our updated SW, and there is not any clock out put except 'LVCMOS OUTPUT0'.
It could be find the EEPROM.hxt always be 0x0000 for 64 words via EEPROM direct read, and can not be modified successfully via both REG commit mode and EEPROM direct mode: when I programming PLL with these two method, TICS Pro logging shows it does write to the REGs and EEPROM successfully, but no any outputs on the 4 channels.
Could you please help to check on the EEPROM.hxt and give some advise about this wrong status?
Thanks in advance.
I've pasted the EETPROM.hxt and our SW programming function here:
+++++++++++++++++++++++++++++++++++++++++++++
----- CDCE6214-Q1 EEPROM HEX TEXT FILE ------
Header Info Tue Jun 14 15:47:06 2022
nvmbusy 0x0001
nvmcrcerr 0x0000
nvm_wr_error 0x0000
nvm_rd_error 0x0000
nvmlcrc 0x0000
nvmscrc 0x0000
nvm_rd_addr 0x003f
nvm_rd_data 0x0000
nvm_wr_addr 0x003f
nvm_wr_data 0x0000
----- BASE PAGE 0 ------
00 0x0000 0
01 0x0000 0
02 0x0000 0
03 0x0000 0
04 0x0000 0
05 0x0000 0
06 0x0000 0
07 0x0000 0
08 0x0000 0
09 0x0000 0
10 0x0000 0
11 0x0000 0
12 0x0000 0
13 0x0000 0
14 0x0000 0
15 0x0000 0
----- CONFIG PAGE 0 ------
16 0x0000 0
17 0x0000 0
18 0x0000 0
19 0x0000 0
20 0x0000 0
21 0x0000 0
22 0x0000 0
23 0x0000 0
24 0x0000 0
25 0x0000 0
26 0x0000 0
27 0x0000 0
28 0x0000 0
29 0x0000 0
30 0x0000 0
31 0x0000 0
32 0x0000 0
33 0x0000 0
34 0x0000 0
35 0x0000 0
36 0x0000 0
37 0x0000 0
38 0x0000 0
39 0x0000 0
----- CONFIG PAGE 1 ------
40 0x0000 0
41 0x0000 0
42 0x0000 0
43 0x0000 0
44 0x0000 0
45 0x0000 0
46 0x0000 0
47 0x0000 0
48 0x0000 0
49 0x0000 0
50 0x0000 0
51 0x0000 0
52 0x0000 0
53 0x0000 0
54 0x0000 0
55 0x0000 0
56 0x0000 0
57 0x0000 0
58 0x0000 0
59 0x0000 0
60 0x0000 0
61 0x0000 0
62 0x0000 0
63 0x0000 0
----- END EEPROM HEX TEXT FILE ------
+++++++++++++++++++++++++++++++++++++++++++
static void pll_reset()
{
char gpio_io_file[128];
sprintf(gpio_io_file, "/sys/class/gpio/gpio%d", gpio_base + gpio_pll);
if (access(gpio_io_file, F_OK) != 0)
{
if ((open_gpio_channel(gpio_pll) != 0) || (set_gpio_direction(gpio_pll, "out") != 0))
{
return;
}
}
set_gpio_value(gpio_pll, 0);
set_gpio_value(gpio_pll, 1);
}
int pll_reg_set(char *file, int i2c_fd)
{
FILE *fp = fopen(file, "r");
if (fp == NULL)
{
printf("fail to open file <%s>\n", file);
return -1;
}
char line[FILE_LINE_LEN_MAX];
char *end_ptr;
unsigned int idx = 0;
while (!feof(fp))
{
fgets(line, FILE_LINE_LEN_MAX, fp);
unsigned int reg_id;
unsigned int value;
sscanf(line, "R%u %x", ®_id, &value);
reg_id = (value >> 16) & 0xffffu;
value = value & 0xffffu;
i2c_write(i2c_fd, PLL_SLAVE_ADDR, reg_id, value);
printf("reg_id:%d, value:0x%x\n", reg_id, value);
usleep(30000);
}
fclose(fp);
return 0;
}
static void pll_config(int i2c_fd)
{
int temp;
/* Write 1 to RECAL to calibrate the VCO in this operation mode */
temp = i2c_read(i2c_fd, PLL_SLAVE_ADDR, 0x0000);
temp = temp | 0x0010;
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x0000, temp);
/* Select the EEPROM page 1, to copy the register settings into, using REGCOMMIT_PAGE.*/
temp = i2c_read(i2c_fd, PLL_SLAVE_ADDR, 0x0003);
temp = temp | 0x0200;
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x0003, temp);
/* Unlock the EEPROM for write access with EE_LOCK = 0x5.*/
temp = i2c_read(i2c_fd, PLL_SLAVE_ADDR, 0x000F);
temp = temp & 0x0FFF;
temp = temp | 0x5000;
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x000F, temp);
/* Start the register commit operation by writing 1 to REGCOMMIT*/
temp = i2c_read(i2c_fd, PLL_SLAVE_ADDR, 0x0003);
temp = temp | 0x0400;
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x0003, temp);
/* Force a CRC update by writing a 1 to UPDATE_CRC.*/
temp = i2c_read(i2c_fd, PLL_SLAVE_ADDR, 0x0003);
temp = temp | 0x1000;
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x0003, temp);
/* Read back the calculated CRC in NVMLCRC.*/
int crc = i2c_read(i2c_fd, PLL_SLAVE_ADDR, 0x0009);
/* Write 0x3F to NVM_WR_ADDR*/
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x000D, 0x003F);
/* Write CRC value to NVM_WR_DATA.*/
i2c_write(i2c_fd, PLL_SLAVE_ADDR, 0x000E, crc);
}
static void pll_init(void)
{
int i2c_fd = i2c_open(PLL_I2C_DEV);
if (i2c_fd == -1)
{
printf("fail to open i2c%d device.\n", PLL_I2C_DEV);
return;
}
pll_reset();
if (pll_reg_set(g_pll_cfgdata_filepath, i2c_fd) != 0)
{
printf("fail to set pll register.\n");
return;
}
pll_config(i2c_fd);
if (i2c_close(i2c_fd) == -1)
{
return;
}
pll_reset();
}
void pll_eeprom_commit(void)
{
int i2c_fd = i2c_open(PLL_I2C_DEV);
if (i2c_fd == -1)
{
printf("fail to open i2c%d device.\n", PLL_I2C_DEV);
return;
}
pll_config(i2c_fd);
if (i2c_close(i2c_fd) == -1)
{
return;
}
}
++++++++++++++++++++++++++++++++++++++++++
And our configuration BTW:
R85 0x00550000
R84 0x00540000
R83 0x0053FF00
R82 0x005201C0
R81 0x00510004
R80 0x00500000
R79 0x004F0008
R78 0x004E0000
R77 0x004D0000
R76 0x004C0188
R75 0x004B8008
R74 0x004AA181
R73 0x00491000
R72 0x00480005
R71 0x00470006
R70 0x00460808
R69 0x0045A181
R68 0x00441000
R67 0x00430004
R66 0x00420006
R65 0x00410808
R64 0x0040A181
R63 0x003F1000
R62 0x003E0004
R61 0x003D0000
R60 0x003C6008
R59 0x003B8008
R58 0x003A502C
R57 0x00391000
R56 0x00380019
R55 0x0037001E
R54 0x00363400
R53 0x00350069
R52 0x00345000
R51 0x003340C0
R50 0x003207C0
R49 0x00310013
R48 0x003023C7
R47 0x002F0380
R46 0x002E0000
R45 0x002D4F80
R44 0x002C0318
R43 0x002B0051
R42 0x002A0002
R41 0x00290000
R40 0x00280000
R39 0x00270000
R38 0x00260000
R37 0x00250000
R36 0x00240000
R35 0x0023005C
R34 0x00220000
R33 0x00212710
R32 0x00200000
R31 0x001F0000
R30 0x001E0064
R29 0x001D0000
R28 0x001C0000
R27 0x001B0004
R26 0x001A0000
R25 0x00190401
R24 0x00181930
R23 0x00170406
R22 0x001600A2
R21 0x00150583
R20 0x00140000
R19 0x00130000
R18 0x00120000
R17 0x001126C4
R16 0x0010921F
R15 0x000FA017
R14 0x000E9AF5
R13 0x000D003F
R12 0x000C7000
R11 0x000B0000
R10 0x000A6BF7
R9 0x00099AF5
R8 0x00080001
R7 0x00070C2D
R6 0x00060A6C
R5 0x00050008
R4 0x00040000
R3 0x00030000
R2 0x00020002
R1 0x00012310
R0 0x00001000
+++++++++++++++++++++++++++++++++
