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CDCE62002 EVM Basic Questions

Other Parts Discussed in Thread: CDCE62002

Hi,

I have the evaluation module for the CDCE62002.

For the default start up conditions - 25MHz at the Primary input, the PLL is in lock.

  1. Can i change the input frequency in the GUI at the Primary input to test if the combination of dividers and other settings will Lock the PLL without having to connect a signal generator to the Primary input SMA ?

I am attempting to use the EVM as a test to ensure that the parameters i have calculated are correct. When i change the input frequency and parameter settings, the PLL does not lock although i meet all the criteria as per the datasheet for parameter settings and boundaries. Hence this question.

Thanks and regards,

Richard.

  •  

    Hi Richard,

    You need to priovide the input clock.

    Have you calibrated the VCO right after register settings? Please calibrate the VCO when you change the PLL settings. Please follow the VCO calibration procedure mentioned in page 34-35 of the datasheet ( March 2011 revision). We have not updated the GUI yet, but just follow the datasheet Register 2 ( R2.13 and R2.20) naming convention. 

    http://focus.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=cdce62002&fileType=pdf

    Thanks,

    Firoj

     

     

  • Hi Firoj,

    Thanks for the reply.

    I will need to create the input clock from a new PCB design - i do not have the relative test equipment at home.

    Another related question ; the register settings for Register 2 that you provided - will i obtain those same or new register settings when using the EVM and with the clock input at 24.576MHz ?.

    As such, i need to use the EVM every time i wsh to calculate and prove the Register 0 and 1 settings, as Register 2 settings are based upon data that is not in the Datasheet (March 2011).

    Thanks and regards,

    Richard.

  •  

     

    Hi Richard,

     

    I am not sure if I understood your question.

     

    You need to program Register 0 and 1. Then you need to use Register 2 just to calibrate the PLL if needed.  

    Thanks,

     

    Firoj

     

  • Hi Firoj,

    Apologies for the late reply - was sidetracked.

    In a previous e-mail you sent - you indicated that besides the standard three bits used for PLL calibration and/or output synchronisation, i need to set the bits including those just mentioned as follows :

    5, 7, 8, 9, 19, 20, 25, and 26.

    These include the calibration and output sync bits etc., but the extras 5, 9, 19, 25, and 26 - why do these need to be set ?.

    Does the EVM provide these - since thy are not specified in the datasheet - and since you have stated set these to logic 1, there must be a reason ?.

    Thanks and regards,

    Richard.

    {As an aside, i have a mechanical issue with my current implementation of the CDCE62002 - so i am re-designing the clock generation circuit as a daughter board - such that if this fails to work - then the entire PCB (280mm x 260mm) is not affected}

  •  

    Hi Richard,

    Yes, you can get the default values from EVM. Right after power up, you can read Register 2.

    I can not  remember if I said to set the mentioned bits to "1".

    You just need to configure  calibration and synchronizing bits keeping the other bits to the default values.  Writing into ready only bits don't matter.

    Bit 0 - 6, 9 - 12  and 25-27 are read only bits.

    Bit 14 - 19 and 21 - 24 are TI internal bits and please keep the default values ( "0")  while writing this register.

    By default, bit 20 is "1" and bit 13 is "0"

    Thanks,

    Firoj

     

     

     

  • Hi Firoj,

    I have copied the screen shot of register 2 you sent to me on 4th May 2011. I assumed a tick in the box was set to logic 1. Is this the output from EVM GUI ?. Thanks and regards, Richard.

     

  •  

    Richard,

     

    Yes, this is from EVM GUI. There are may read only bits in Register 2 and these value can be changed based on operating conditions.

     

    Thanks,

    Firoj

     

  • Thanks Firoj,

    Much appreciated.

    Regards,

    Richard.