CDCI6214: ZDM usecase

Ryuuichi machida

Part Number: CDCI6214

Hello,

I would like you to confirm whether I can use following use.
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Usecase :
* Input is 25MHz LVDS.
* Output is 2x 125MHz LVDS.
* power supply for all VDDxx is 3.3V.
* use ZDM with internal FB

Q. Is my understanding that we can conpensate between input clock(REFP/N (external reference clock) and both 2 output clock correct ?
(According to datasheet, it seems internal FB mode can be used only for output of ch2. So, in my case when we use ch1 and ch2 as 2 output clock. FB from ch2 output to PLL is available and expect to align input clock phase and 2 output clock phase.(not only ch2 clock but also ch1 clock))
--

BR,

over 3 years ago

0 Julian Hagedorn over 3 years ago

TI__Mastermind 20900 points

Hello Ryuuichi,

you can have the outputs aligned while using ZDM mode. You will have to sync the output dividers for this.

regards,

Julian

0 Ryuuichi machida over 3 years ago in reply to Julian Hagedorn

Guru 12620 points

Hello Julian-san,
Thank you for your reply.
>you can have the outputs aligned while using ZDM mode. You will have to sync the output dividers for this.
Is there any way to sync output dividers ?
(According to datasheet, there are two dividers. Should user use 5 bit delay(chX_sync_delay) to sync two output by referring output clock ?)

BR,

0 Julian Hagedorn over 3 years ago in reply to Ryuuichi machida

TI__Mastermind 20900 points

Hi Ryuuichi,

i have to correct myself. You don't need a sync. You can use CH2 output divider for feedback. Then you select CH2 in the ch1_mux or ch3_mux register.z

With that both outputs are in sync.

Regards,

Julian

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CDCI6214: ZDM usecase