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LMK03328: NVMCRCERR

Kazumi Kato
Prodigy 10 points
Part Number: LMK03328

Hi, support team

We are developing broadcasting FPGA board using LMK03328.

The LMK03328 is operating in soft pin mode.

The other day, a trouble occurred at the delivery destination this board(Delivered in April 2020).

I checked this board and found NVMCRCERR is H at LMK03328.

NVMCRCERR is cleared by overwriting EEPROM,but I don't know what is caused EEPROM data garbled.

Please tell me the cause EEPROM data garbled and NVMCRCERR.

By the way, Writing to EEPROM is not performed at the delivery destination.

Regards.

  • 0
    TI__Expert 8585 points

    Hello Kazumi,

    The root cause is the voltage margin at which the EEPROM data is being written to the device.

    When writing data to the EEPROM of the device, there is a voltage threshold (0.8 V) that determines if the data being written is high (1) or low (0). For the corrupted addresses, the voltage being applied to the FET that determines the data’s state may be close to the threshold and therefore corrupting that addresses resulting state.

    Irrelevant of whether the EEPROM is being written to or not written to, the device must first clear CRC before proceeding with any start up sequence (calibration, etc.). This is because the device is being booted up in EEPROM mode. Therefore, since we can’t clear the CRC, we are getting a device that’s non-functional.

    The solution to this issue is to perform one of the following:

    1. Re-program the EEPROM as you have done.

    2. Boot up in hard pin mode (HW_SW_CTRL = 1).

    Regards,

    Kia Rahbar

  • 0 in reply to Kia Rahbar
    Prodigy 10 points

    Hi Kia,

    Thank you your support.
    If the voltage applied to the FET at the time of writing is close to the threshold value, does it mean that there is a possibility of garbled data at the time of writing to EEPROM?

    IF so,Is there a way for the user to ensure a sufficient voltage well above the threshold when writing to EEPROM?

    I know hou to clear the CRC error.
    Thank you.

    Regards.

  • 0 in reply to Kazumi Kato
    TI__Expert 8585 points

    Hello Kazumi,

    Unfortunately, I am not able to provide a detailed explanation for the root cause at this time. The above explanation is what I have received from our design team and a full analysis of the root cause from our design team will not be available until the end of August/ early September.

    Our design team has confirmed that re-programming the EEPROM or booting up in ROM mode will solve the issue and result in no degradation in device performance.

    I can provide a detail explanation of the root cause once our design team has done a deeper dive into the issue.

    Apologies for the inconvenience.

    Regards,

    Kia Rahbar 

  • 0 in reply to Kia Rahbar
    Prodigy 10 points

    Hi Kia,

    Thank you for your reply.

    It doesn't matter if it's past September,I would like a detail explanation of the root cause.

    Regards.

  • 0 in reply to Kazumi Kato
    TI__Expert 8585 points

    Hello Kazumi,

    Sounds good. I will update you in September.

    I will be closing this thread for now and will reopen it when I have the detailed explanation.

    Regards,

    Kia Rahbar