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LMX2572: can not lock when fpd is changed to100MHz

John Jiang1
Prodigy 100 points
Part Number: LMX2572

I need to scan frequency (13MHz ~ 3GHz) with LMX2572 with switching time < 15uS (it is better < 10uS) for each freequency. My Osc input is 50MHz and fpd is 50MHz. With full assist mode, it takes 15uS to lock ( with 70MHz SPI clk). According to the datasheet, with 100MHz fpd, the lock time is ~5uS in full assist mode. So I enabled the doubler so that fpd is 100MHz, but then LMX2572 failed to calibrate (R0 is 0x231C). But if I enable Post-R with divider of 2, so that fpd becomes 50MHz again, the auto calibration works fine. PLL_N, PLL_NUM, PLL_DEN, CHDIV  are calculated correctly with my firmware routine. It seems that no other register changes needed for auto calibration to get read back values when fpd is changed. So I think it might be loop filter. The loop filter is exactly the same as EVM board (C1,C3 open, C2 15nF, C4 2.2nF, R2 330 Ohmn, R2, R4 0 Ohm), and the EVM has examples of using both 50MHz and 100MHz as fpd. So it seems loop filter should work as well. Can you please help me figure out why auto calibration failed with 100MHz? Also to reduce the lock time with full assist mode, is there any other way? I already set LD_DLY to 0 and only sends the REGs whose value are changed when switching. It seems that increasing charge pump current can also help a little bit, is there any negative side to do that? Thanks for reply.

  • 0
    TI__Guru** 107090 points

    Hi John,

    The (auto) VCO calibration time depends on the state-machine clock which is equal to fosc / 2CAL_CLK_DIV. Full assist mode does not need calibration, there is no calibration time, the 5µs "calibration" time is the sum of register response time and LDO response time. As such, the reference clock frequency is not matter at all. Loop filter is important for PLL's response time for a frequency change. If you want faster lock time, loop bandwidth should be wide; phase margin around 50deg; gamma factor close to 1. You can use PLL Sim to design the loop filter.

    VCO calibration was performed in an open-looped environment, as a result, the calibration data does not depend on fpd. You can use the same calibration data in full assist mode with fpd = 50MHz or 100MHz.

    I don't know why you cannot get auto calibration works at  fpd = 100MHz, was FCAL_HPFD_ADJ = 0x2 with 100MHz fpd?

  • 0 in reply to Noel Fung
    Prodigy 100 points

    Noel, thanks for the quick reply. I just found that I had a typo in code which caused the problem at 100MHz. Now 100MHz works fine and the lock time improved (from MUX out on scope). The lock time is improved from 15uS to ~12uS when fpd is changed from 50MHz to 100MHz. At 100MHz, then I adjusted the charge pump current from default 2500uA to max 6875uA, the lock time is improved from ~12uS to ~5uS which matches the datasheet specs. Is there any negative side to keep highest charge pump current?

  • +1 in reply to John Jiang1
    TI__Guru** 107090 points

    Hi John,

    fpd spurs will be higher with higher charge pump current. 

    Since the original loop filter was design with 100Mhz fpd and 2.5mA current, if you increase the current, loop bandwidth will be higher and usually lock time will be smaller. However, you need to make sure the phase margin is still good with this setting. Use PLL Sim to verify and re-design your loop filter.

  • 0 in reply to Noel Fung
    Prodigy 100 points

    Hi, Noel:

    I did additional testing by using FPGA to catch the max delay during switching frequencies every 250uS (FPGA saves the worst delay during whole testing time). In the first test, it switches between 13MHz and 14MHz, and the worst delay is ~6uS for about 10 seconds; after 1 minute, the delay can be as high as 70uS. In the second test, the frequency changes from 13MHz to 1300MHz with step of 1MHz, and the worst delay is ~27uS for 10 seconds; after 10 minutes, the worst delay FPGA caught is 150uS. I would expect the lock time won’t change that significantly since everything is defined and should be repeatable. What can be the reason of different lock time with the same frequencies? Any way to solve the problem? Thanks.