LMK00304 only has the Additive RMS Jitter parameter of 1MHz to 20MHz in HCSL output mode, is there any Additive RMS Jitter parameter of 12KHz to 20MHz (or 10KHz to 20MHz)?
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LMK00304 only has the Additive RMS Jitter parameter of 1MHz to 20MHz in HCSL output mode, is there any Additive RMS Jitter parameter of 12KHz to 20MHz (or 10KHz to 20MHz)?
Hello,
the datasheet has 3 lines of additive jitter specification. Please see the first line:
Regards,
Julian
Hello,
The table that Julian posted is actually for LVPECL output mode. For HCSL with an integration bandwidth of 12KHz to 20 MHz, additive jitter is typically 48 fs.
Regards,
Connor
Thanks a lot. For another question,I can't find the time parameter from the power-on to the buffer stable output clock in the LMK00304 specification. We have clear timing requirements (<10ms) in our design. Can you provide the relevant parameters, thank you.
Hello,
After stable VDD the outputs will output a signal after "tpd" (propagation delay time) when the signal is applied to the inputs.
The stability/accuracy of the output clocks are determined by the input source.
Regards,
Julian