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LMK03328: Maximum jitter for the input clock

ttd
Mastermind 8610 points
Part Number: LMK03328

Dear Technical Support Team,

My target device is LMK03328.

What is the maximum jitter for the input clocks (PRIREF_P / N and SECREF_P / N)?

The maximum jitter for the input clock was not found in the datasheet.

Best Regards,

ttd

  • 0
    TI__Genius 12560 points

    Hi ttd,

    The datasheet doesn't specified the input clock jitter but you could optimized the input clock jitter for required output clock jitter requirement using the PLLatinum Sim tool.

    Thanks!

    Regards,

    Ajeet Pal

  • 0 in reply to Ajeet Pal
    Mastermind 8610 points

    Hi Ajeet Pal,

    Thank you for your reply.

    I check PLLatinum sim tool and it seems to use just OSC below.

    Does it have LVDS(Differential) and LVCMOS(Single-End) for (PRIREF_P / N and SECREF_P / N)?

    Best Regards,

    ttd

  • 0 in reply to ttd
    TI__Genius 12560 points

    Hi ttd,

    LMK03328 having OSCin as PRIREF or SECREF for the PLLs, hence OSC noise in PLLatinum Sim tool can be consider for these input reference only.

    You can enter as use metrices or load the phase noise data of the expected input signal and can simulate in PLLatinum sim tool.

    Thanks!

    Regards,
    Ajeet Pal