CDCE937: Out clock phase drift

I want to use the CDCE937 to generate four output clocks that will need to be in phase will each other.

27MHz in, 27MHZ, 148.5MHz, 200MHz and 212.5MHZ out. I see from the design tool that these clock can be generated with a zero ppm error.

What is the phase drift of the output clocks w.r.t. each other?

Thank you

Dave R