CDCI6214: About the reference clock to PLL issue.

Hi expert,

My customer wants to use a single-ended LVCMOS 50MHz clock as reference clock at CDCI6214.

There are 2 questions about the ref. CLK.

1. When setting CLK Input to REFP/N :

REFP/N are differential pins, how to deal with external single-ended input clock?

Does it can use a balun to transfer single-ended-to-differential?

2.  Also I notice that XOUT can use single-ended LVCMOS input.

CLK Max. =50MHz, it will be very close to the limit frequency in datasheet, do you recommend work with this way? 

3. In this case, could you please give us some advice?

Thanks.