LMX2485E: Slow charge pump output slew rate

Simon Delaney

Part Number: LMX2485E

I'm using the RF side of an LMX2485E PLL in a design with a passive discrete loop filter and a discrete VCO. I've modelled this all in the PLLatinum tool, which shows reasonable results, but measurements of lock time do not match up.

For small voltage/frequency changes the lock time is similar to the model, but for larger changes there seems to be a slew rate limit on the voltage on the PLL charge pump/loop filter output. The voltage is a linear slope between one frequency and the next, the slope is proportional to the charge pump current (double the CP current = twice as fast a slope).

I've never seen anything like this before with a PLL, and cannot point to any features of the circuit that might cause this. CSR does not seem to help at all.

Has anyone else seen this behaviour? Can you suggest anything that might cause this effect?

over 4 years ago

0 Noel Fung over 4 years ago

TI__Guru** 120220 points

Hi Simon,

I guess this is due to cycle slipping. Is your fpd much higher than the loop bandwidth?

0 Simon Delaney over 4 years ago in reply to Noel Fung

Prodigy 20 points

It is much higher, yes, but turning on CSR makes very little difference, changing the loop bandwidth (significant filter change) makes very little difference.

I did try halving the phase detector rate and didn't see much change. I could try dropping it a lot further, but the PLL noise is already fairly high from this IC and degrading it further isn't a good option.

0 Noel Fung over 4 years ago in reply to Simon Delaney

TI__Guru** 120220 points

Hi Simon,

Could you share your PLL Sim design? I would like to see if there is room to improve.

0 Simon Delaney over 4 years ago in reply to Noel Fung

Prodigy 20 points

Unfortunately probably no, I don't think I can. Replicating the design in ADISimPLL (obviously with a different IC, but a similar one), does show cycle slipping in the time domain response, so I suspect it is a cycle slipping issue.

It would be helpful if the PLLatinum tool could show cycle slipping behaviour - is that something it could/should do if I select the right options, or does the tool not simulate that behaviour?

0 Noel Fung over 4 years ago in reply to Simon Delaney

TI__Guru** 120220 points

Hi Simon,

PLL Sim does support cycle slipping simulation in Discrete Lock Time Model.

FYI, we have the user's guide for PLL Sim, it is available from the Help menu bar.

0 Simon Delaney over 3 years ago in reply to Noel Fung

Prodigy 20 points

Thanks, I've found the discrete model and yes, it does show cycle slipping. Unfortunately, the simulated results are not consistent with the observed behaviour of the hardware.

I have a few ideas to try in the hardware to try and fix this problem now I know what's going on.

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LMX2485E: Slow charge pump output slew rate