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Clock Buffer for CDCE62002 Outputs

shadders
Expert 1065 points
Other Parts Discussed in Thread: CDCE62002, SRC4392, PCM1792A, CDCLVC1102, SN65HVD10

Hi,

I am using the CDCE62002 to produce clock signals for an Audio DAC - and i am now implementing the clock circuit on a daughter board to ensure that if the CDCE62002 fails to be soldered correctly, that the entire DAC board is affected.

I have two PCM1792A's in the new design - one for each channel. i am planning to you SMA connectors from the clock daughter board to the PCM1792A IC's, and thus require two clock outputs. Being a purist, i did not want to clock the PCM1792A IC's with alternate phase clocks from the CDCE62002 output (the other output is clocking the SRC4392).

Hence - i want to use a clock buffer to utilise the positive clock 0 output to send to both PCM1792A IC's.

Which is the preferred clock buffer that does not degrade the low clock jitter of the CDCE62002 ?. Thanks. (CMOS ACT logic ???)

Another related question - i wish to convert the TOSLink output which is a single ended signal to a differential signal which will eventually be connected to the SRC4392 Sample Rate Converter. The length of PCB track will be up to 30cm long - hence the reason for buffering and differential conversion.

Can anyone again suggest a suitable buffer - will standard ACT CMOS logic be acceptable ?.

Thanks and regards,

Richard.

  • 0
    TI__Expert 3985 points

    Hi Richard,

    since you want to use the positive clock 0 output of our CDCE62002, I would assume that you are using an LVCMOS clock output signal. If this is the case, I could suggest you to use in your system our CDCLVC1102: this is a general clock buffer which rounds up an LVCMOS input to two LVCMOS output. Its additive jitter is less than 100fs, as specified in the datasheet.

    About your 2nd question, could you please provide us the single-ended signal levels of the TOSLink output?

    Thanks and regards,

    Leandro

  • 0 in reply to Leandro_z
    Expert 1065 points

    Hi Leandro,

    Thanks for the reply.

    I will examine the CDCLVC1102 - i think i can use two SMA connectors and coaxial cables rom the clock board to the main circuit board from one output as both PCM1792A input circuits are CMOS. I can always update the clock board with the IC for later versions if there are issues.

    For the TOSLink IC - this is CMOS 3.3volts output - but i found a suitable IC which is the TI SN65HVD10 which has a bit rate of up to 32MB which is more than double that of the optical receiver. The use of a differential transmitter to the SRC4392 will assist in the placement of components closer to the PCM1792A IC's.

    Thanks again for your response, much appreciated.

    Regards,

    Richard.

  • 0 in reply to shadders
    TI__Expert 3985 points

    Hi Richard,

    just a quick update. The CDCE62002 can provide also two LVCMOS in-phase outputs. Meaning that U0P and U0N can be set as two in-phase LVCMOS output. If you are running out of space in your board, you could even use this solution.

    Best Regards,

    Leandro

  • 0 in reply to Leandro_z
    Expert 1065 points

    Hi Leandro,

    Thanks - i think i was mis-interpreting the data sheet - since U0N and U0P are differential for non-CMOS settings, i assumed that they were also in 180-deg out of phase for LVCMOS. Hence if they are both in phase - i will use both outputs - one for each PCM1792A .

    Thanks and regards,

    Richard.