LMK03318: PLL occasional loss of lock

Hi Jordan, 
I'll look at this in more detail tomorrow. One thing I did notice is that the VCO frequency is extremely high? 12.5Ghz is a little more twice the maximum VCO frequency. Input is secref just to confirm? 

Hi

Input should be 10MHz, and VCO should be 5GHz. I've attached the exact settings file I am running on the EVM in case something loads incorrectly from the raw registers I sent. 

Thanks

Jordan

pro_settings_defaults.tcs  

Hi Vicente

Thanks for your reply. The input clock is stable, and the power is being provided by the LMK03318 evaluation board itself (I supply stable 5V >1A supply, then the LMK03318EVM drops down voltages as needed). Would there be any issue with the LMK evaluation board design that was cause power stability issues?

Thanks

Jordan

Hi Jordan, 
There are no issues. What is the input, SigGen, XO, or onboard XTAL? 

Regards, 

Vicente

Hi Vicente,

The testing so far has been with external input from a signal generator. I'm now testing with the onboard 50MHz crystal but have so far not seen it go unlocked.

Regarding our external signal source, I have a 100MHz signal generator generating a 10MHz square wave, which is converted to a differential signal with a 0-180 degrees RF splitter. This is AC-coupled into the LMK eval board PRIREF SMA inputs. The signals are 800mVpp each (so differentially 1.6Vpp). When testing with this config I have the settings as below, with differential termination and AC_MODE enabled. With these settings I am still seeing the PLL go unlocked.

Hi Vicente

In our configuration the R divider is set to 1, so it seems I can't get an output on PLL RDIV/2 as suggested. If I turn on the R divider and set to 2 (and double my input frequency correspondingly) I can see the RDIV/2 signal on the status pin. I have left this running for about 36 hours and could not see it lose lock at all. My two test comparisons are:

• 10 MHz input, RDIV=1, PFD=10MHz -> PLL loss of lock after several hours
• 20 MHz input, RDIV=2, PFD=10MHZ -> no loss of lock after 36 hours

Is there any reason that the performance would be better with RDIV=2 vs RDIV=1 (bypassed)? The next test I will run is with a 10MHz input again, and run it at a 5 MHz PFD with RDIV=2.

Thanks

Jordan

Hi Jordan, 
I plan on running your tics pro file you sent previously and wait a few hours to see if I lose lock. What results did you for the next test? 
I'm going to need some time to determine if their is a design explanation why performance is better with RDIV=2 vs RDIV=1

Regards, 

Vicente

Hi Vicente,

That would be great thanks, we are just doubling checking our results before getting you to replicate. Note that in some cases it can take several days to lose lock.

In some cases we have had CAL_INTR be flagged, but not LOL_INTR. Could you provide insight on what the CAL_INTR refers to, and why it may be flagged?

Thanks

Jordan

Hi Vicente

What would cause CAL interrupt source to detect an edge? I can't find any more info about this in the datasheet - could you clarify what error would cause CAL_INTR (or what error it could indicate is occuring)?

Thanks

Jordan

Hi Jordan, 

So I recently found out these status bit's don't function properly on LMK03318. 
If you are indeed still losing lock, it is a possibility the PLL is unstable. Are you using the appropriate C2 value? This is an external capacitor. 

Regards, 

Vicente

Hi Vicente

Could you clarify which status bits don't function properly? Just the CAL_INTR ones, or also the LOL/LOS status bits?

We are using C2=3.3nF (3300pF)

Hi Vicente

That's quite concerning that the status bits don't work - can you provide more info on why they don't work? We are currently relying on these sticky indicators to detect the loss of lock.

I can't see R151 in the datasheet or in the GUI - is that a special register? What does R151 tell us exactly compared to the normal status bits in register R13?

Thanks,

Jordan

Hi Vicente

When I read back from R151 in our design, I get 0x88, so bit 5 is 0. What does this tell us, is there any special reset required?

I am reading this out on our custom board design using the LMK03318 - is there a way I can also check on the EVM? R151 doesn't seem to exist as an option to read back in the TICS Pro software.

Thanks,

Jordan

Hi Jordan, 
Yes, it appears the device is not power up correctly thus the PLL doesn't properly lock. Have you done an ABA swap as follows? 

Hi Vicente

We suspect this is happening on all of our boards, so don't have a 'good' part to swap in. 

How about testing this on the EVM? Is there a way to read back custom registers through the TICS software?

Thanks,

Jordan

Hi Vicente

Yes we have seen this issue on our custom board, running the same settings and configuration that we are testing on the evaluation board.

We are in the process of trying to replicate our results on the evaluation board with a different reference source that can meet the slew rate requirements of the LMKs PRIREF and SECREF inputs. On our custom board we are meeting this requirement comfortably.

Regarding R151.5 readback, we see some boards read back as 0, some as 1. Is this bit purely relating to power on, or is it at all related to reset sequencing? Are there any other special registers we could look at, or could you share that document that you found R151.5 mentioned?

Thanks

Jordan

Hi Vicente

Is there anything design wise we should look at to explain why R151.5 is 0 for us? The datasheet does not specify particular requirements for power sequences - is there anything we should check in our design?

Thanks

Jordan

Hi Vicente

I have checked R151.5 on the EVM as well by using our own I2C dongle, and it reads back as 0 as well. Could you please confirm if this is expected?

Thanks

Jordan