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cdce62005 configuration value

kim kwang joo
Prodigy 110 points
Other Parts Discussed in Thread: CDCE62005

hi.

i  provided the 25Mhz clock to the AUX_IN.

As a ouptut, i want to get the 50Mhz LVDS clock at the output 0, 1, and 25Mhz LVDS clock at the output 2, 100Mhz LVDS clock at the output 3,4.

When the register value got from the CDCE62005 EVM software is configured to the chip,

the Output of the CDCE62005 is not exactly matched to the 100Mhz, 50Mhz, 25Mhz.

Configured register values are

#define REG0_VAL  0xeb05ffef 
#define REG1_VAL  0xeb05ffff 

#define REG2_VAL  0xeb0c03cf
#define REG3_VAL  0xeb85ffef
#define REG4_VAL  0xeb85ffff 
#define REG5_VAL  0x7c00ff3f
#define REG6_VAL  0xa70f010f
#define REG7_VAL  0xfda975ef

I wan to know the register values for the 100Mhz LVDS output or how to configure the loop filter.

best regards

KJ

 

  

  • 0
    TI__Expert 3985 points

    Hi Kwang Joo

    sorry for the late reply to your post. We are currently trying to reproduce your issue in our lab. We would like to have some additional info.

    Is the 25MHz signal at AUX_IN provided by a crystal or by a LVCMOS clock signal?

    If needed, you can configure your loop filter by the Loop Filter Tool available on the CDCE62005 EVM software GUI.  According to your specific application, you can select there the desired loop bandwidth and phase margin. The tool generates the component values that you need to use.

    Best regards,

    Leandro 

  • 0 in reply to Leandro_z
    TI__Expert 3985 points

    Hi KJ

    here is still Leandro. I came out with some setting which may be useful for you, in case the AUX_IN pin is fed by a 25MHz crystal. In attachment you find a ppt with some screenshots about the GUI interface and the register settings, I used to get a lock condition for the PLL.

    Best Regards,

    Leandro

    CDCE62005 setting.ppt
  • 0 in reply to Leandro_z
    Prodigy 110 points

    Hi Leandro

    we were testing with your setting value.

    but we could not get the frequency matched.

    our board is produced the following frequency.

    Output0, 1 : 46.4Mhz

    Output2 : ??

    Output3,4 : 92.8Mhz

    why is the frequency not matched with setting value?

     

    best regards

    KJ

     

     

  • 0 in reply to kim kwang joo
    TI__Expert 3985 points

    Hi KJ

    we do see the same frequency value (46.4MHz and 92.8MHz) if we do not perform any calibration.

    I have some more question: are you using our EVM to perform measurment? If you are using another board, could you please send us a schematic? If you are using our EVM, I guess you are using the GUI interface for our device as well. If you click on the VCO block a window will pop up called "VCO settings". Could you please select the "Enable Auto VCO" feature and try to do again the measurement? By the way, you can perform a calibration by clicking on the Calibrate bottom on the GUI.

    Best regards,

    Leandro

  • 0 in reply to Leandro_z
    Prodigy 110 points

    3632.08. Clock _ 08.pdf

    Hi leandro.

    we are using the our board.

    refer to the attachment file.

     

    best regards

    KJ

     

  • 0 in reply to kim kwang joo
    TI__Expert 3985 points

    Hi KJ,

    sorry for not fast reply. If you are using your own board, you have to perform the calibration manually. You can refer to table 12 and table 15 on the datasheet. Anyway, I suggest you a way to do that.
    Basically you have to set the ENCAL_MODE bit (register 6, bit 27) to HIGH and then apply a LOW to HIGH transition on ENCAL bit (register 6, bit 22). This means that you have to write on the register 6 first:

    step 1) 0x825e03e6

    and then

    step 2) 0x865e03e6

    Best regards,

    Leandro

    Note: please take care of writing the LSb first on the SPI buffer like depicted on figure 14.