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CDCE6214: Some Questions on EEPROM Page 0 Initialization/Startup

Darren (FAE)
Expert 5483 points
Part Number: CDCE6214
Other Parts Discussed in Thread: CDCI6214

I understand the CDCE6214 (CDCI6214) both support 4x 100MHz HCSL outputs by default.

Q1:
From Fig. 29 in the datasheet, it looks like the only requirement to load page 0 defaults and get this output without programming, is to pull pin23 LOW, right?
Pins 11/12/19/20 become the output enables, and pin 8 toggles RESET, right?

Q2:
The startup process looks like this, right?
1) Pull pin23 LOW on the PCB
2) Supply power to VDDVCO; keep RESETN LOW until VDD reaches 95% of final value
3) After RESETN voltage rises above 0.8 × VDDREF, device is released from RESET and depending on the OEx pin level, outputs 100MHz HCSL on Y1~Y4.

Q3: 
I understand a 25-MHz LVCMOS clock can be input to XOUT(pin1) instead of a crystal.
Should pin2 be connected to GND or left floating? CDCEx datasheet mentions connecting to GND, but CDCIx has no comment on this.

Q4: 
pin4 (REFSEL) needs to be set LOW to use pin1 as the LVCMOS clock input (25MHz), right?

Q5:
"Typical Applications" figure in both datasheets show pin23(EEPROMSEL) and pin4(REFSEL) being pulled LOW through 4.7k resistors.
Why this value? I understand internal to these pins there are 50k PU/PD resistors; so couldn't you just tie them to GND? Any reason this was not the described use-case?

Q6.1:
Regarding Enabling/Disabling the outputs.
It looks like there is an internal 50k PU resistor on OEx pins, so if the pins are left floating, the channels are automatically enabled, right?

Q6.2:
If you wanted to disable any of the outputs, you need to pull the corresponding OEx pin LOW, right?

  • 0
    TI__Genius 16615 points

    Hi Darren,

    We'll get back to you tomorrow. I apologize for the delay.

    , please assist with these questions.

    Regards,

    Jennifer

  • 0
    TI__Mastermind 29362 points

    Hi Darren, 

    1. Correct pull pin LOW low to load EEPROM page 0. Yes Pins 11/12/19/20 become the output enables, and pin 8 toggles RESET. 

    2. That is correct. 

    3. If Xout is used but not Xin, tie Xin to GND to ensure no crosstalk. If Xout nor Xin are used both can be left floating as input will be ignored at clock selection MUX.  

    4. Correct, set to low so MUX choose single ended input clock. 

    5. The reason for this is both of these pins are tri-state pins. It allows users to either choose high or low whereas internal resistors are used to generate the voltage level for the "mid" state. Why 4.7k Ohm value is chosen I need to double check with team. I will get back to you on this one. 

    6.1 I will need to check with team tomorrow for this one as well, if I'm not mistaken pin cannot be left floating and must be connected to VDDREF through resistor. 

    6.2 To disable any of the outputs, set to high. 

    Regards 

    Vicente 

  • 0 in reply to vicente flores prado
    TI__Mastermind 29362 points

    Hi Darren, 

    I have checked with the team and have updates. 
    5. The reason 4.7Ohm resistors are chosen due to the resistors size being large enough to limit the current, but strong enough to pull the pin high. 

    6.1. Yes, can be left floating and the channels are automatically enabled. 

    Regards, 


    Vicente 

  • 0 in reply to vicente flores prado
    TI__Expert 5483 points

    Hi Vincente,

    vicente flores prado said:

    6.2 To disable any of the outputs, set to high. 

    Please double check; pins 11,12,19,20. 

    Rising Edge(high) = Enabled
    Falling Edge(low)  = Disabled

  • 0 in reply to Darren (FAE)
    TI__Mastermind 29362 points

    Hi Darren, 

    Correction, should be set to low. 

    Regards, 

    Vicente

  • 0 in reply to vicente flores prado
    TI__Expert 5483 points

    Hi Vicente,

    I would like to confirm one more time on the following application / use-case please.

    From the Datasheet: 

    The device is factory-configured to provide:
    ・100-MHz LP-HCSL with 25-MHz XTAL and HW_SW_CTRL = H. The 25-MHz output on OUT0 is enabled.

     Questions: 

    Use-Case:
    Input: 25MHz LVCMOS Clock Signal into PRIREF_P
    Output: 100MHz LP-HCSL (output to OUT1,OUT2,OUT3,OUT4) used for PCIe REFCLK applications

    1) No need to program EEPROM, correct?
    2) PRIREF_N can be connected directly to GND (as PRIREF_P is receiving LVCMOS clock signal)
    3) HW_SW_CTRL = 4.7k PU required?
    4) REFSEL = 4.7k PU required?
    5) If OUT0 and/or OUT4 is not required for a certain application, can the pin(s) be left floating?
    Since they will be outputting a clock by default using pin-mode configuration, would terminating the pin with PD be better? If so, why?
    6) How should the unused SDA/SCL/GPIO pins be terminated? Can they be left floating?

    Edit:
    I recall hearing that CDCE6214 and CDCI6214 were supposed to be the same in all functionality;
    except basically one was HCSL and the other LP-HCSL.
    But CDCI6214 vs CDCE6214 datasheets show discrepencies in the page0 and page1 settings.

    Is this statement from CDCE6214 datasheet (p40) accurate?

    The device is factory-configured to provide:
    • 100-MHz LVDS with 25-MHz XTAL when HW_SW_CTRL=L. The 25-MHz output on OUT0 is enabled.
    • 100-MHz LP-HCSL with 25-MHz XTAL and HW_SW_CTRL = H. The 25-MHz output on OUT0 is enabled.

    I thought HW_SW_CTRL = 0 set all outputs (OUT1~OUT4) to LP-HCSL; but this statement says "0" results in LVDS and OUT0 (25MHz) is enabled?
    This is different from p29 which says HW_SW_CTRL = 0 will load Page0 (which is 4x HCSL outputs)

    Can you double check and confirm this for me?

    Regards,
    Darren

  • 0 in reply to Darren (FAE)
    TI__Mastermind 29362 points

    Hi Darren, 

    1. Correct, no need to program EEPROM as this config is EVM default. 

    2. Correct, connect PRIREF_N to GND. 

    3. The HW_SW_CTRL can be pulled either low or high if EEPROM is used, or kept floating if EEPROM is unused. 

    4. Correct, PU resistor required otherwise it'll select SECREF as input. 

    5. Yes, just leave floating. 
    6. Yes, leave unused SCA/SDL/GPIO pins floating.

    That appears to be a mistake, setting low enables HCSL. 

    Regards, 

    Vicente 

  • 0 in reply to vicente flores prado
    TI__Expert 5483 points

    Hi Vincente,

    Could you comment on the below as well please?
    (Questions all consider pin23 pulled LOW for 4x HCSL 100MHz outputs)

    >> pin4 under the following termination will select which reference input channel; with pin23 pulled LOW?
    PU = pin5/6
    PD = pin1/2
    Floating = Tri-State = pin1/2? Or does something else happen? Will EEPROM load Page 0 okay?

    >> pin7 is High-Z by default right? It won't output any clock signals and can be left floating?

    >> Sorry to confirm again, but the only differences in this use-case between CDCE6214 and CDCI6214 is the external termination requirement, right?

    >> Assuming an application where you were setting the device via I2C, you would need completely different S/W, right?
    (CDCE6214 and CDCI6214 Register Tables (Table 22 and Table 13 in their datasheets) don't align the addresses / bits)

    >> The values of the following bits in registers like R60, R66, R71 and R76 aren't the same when EEPROM Page 0 is used.
    DIFBUF_IBIAS_TRIM
    LVDS_CMTRIM_INC
    LVDS_CMTRIM_DEC

    Can these settings be ignored since the default is LP-HCSL? Or are they impacting the operation of HCSL?

  • 0 in reply to Darren (FAE)
    TI__Mastermind 29362 points

    Hi Darren, 

    Of course. 

    Pin 4 will select SECREF for reference input.  But why are there PU connected to PRIREF?  If REFSEL is pulled low, SECREF is the input. PRIREF_P/N should both be left floating. These are input pins and should not have PU/PD in the case they're not being used, the unused inputs should be left floating. 

    Correct, OUT0 won't output anything and can be left floating. 

    Correct, only difference here is the external termination. 

    Correct, these are different S/W. Just note, to program via I2C SDA AND SCL must be configured appropriately. SDA and SDL both require external PU to VDD_REF. 

    They can be ignored here as they don't affect HCSL operation. 

    Regards, 

    Vicente