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LMK04826: LMK04826 for JESD204C link can't establish if SYSREF divide from VCO

Eddie Chou
Expert 6180 points
Part Number: LMK04826
Other Parts Discussed in Thread: LMK04828, ADC12DJ5200RF, LMK04821

Hi Team,

My customer is using LMK04826 provide JESD204C REFCLK  for FPGA , but got some problem with JESD204B link,

1.  The original design(ref. to  picture)：

FPGA：ZCU106

Clock generator：LMK04826

Source：TCVCXO 125MHz

VCO0：1875MHz

REFCLK：VCO0/6=312.5MHz

Sync problem(ref. to  picture)：use above setting provide REFCLK to FPGA, but Sync waveform is toggle , cannot get JESD204C link 

2. customer modify LMK04826 setting below

FPGA：ZCU106

Clock generator：LMK04826

Source：Signal generator 312.5MHz

VCO0：No used

REFCLK：Signal generator Bypass=312.5MHz

Conclusion：provide REFCLKt o FPGA and Sync is always high & JESD204C become link

3. modify our to another design as setting below (ref. to  picture)：

FPGA：ZCU106

Clock generator：LMK04826

Source：TCVCXO 125MHz & Signal generator 312.5MHz

VCO0：1875MHz

REFCLK：Signal generator Bypass=312.5MHz

Conclusion：provide REFCLK to FPGA and Sync is always high & JESD204C become link

below are questions from customer,

1. why 312.5MHz REFCLK divide from VCO0 will cause JESD204C sync. toggle and link can't establish?

2. base on #3 modification, does 125MHz & 312.5MHz need synchronization?

3. customer check our ADC12DJ5200RF EVM+ TSW14J57 reference design, REFCLK is also not divide from LMK04828 VCO, is it correct?

Thanks & Regards

Eddie

  • 0
    TI__Genius 12560 points

    Hi Eddie,

    What are the other clocks generating from LMK04821? Please specify the frequencies. They should be integer division of selected VCO0 frequency.

    Config 1:

    Does the PLL2 locking in this configuration? if it is not locked, can get different clock out frequency and there wont be JESD204C link establish. 

    Please share the config file for debug on this.

    Eddie Chou said:
    2. base on #3 modification, does 125MHz & 312.5MHz need synchronization?

    If the other clocks are SYSREF and going to FPGA, also if REFCLK is for FPGA (312.5MHz), then 312.5MHz and SYSREF out should be from same source or aligned to each other.

    Please help to provide the exact clocking block diagram for recommending the clock sequence/configuration.

    Eddie Chou said:
    3. customer check our ADC12DJ5200RF EVM+ TSW14J57 reference design, REFCLK is also not divide from LMK04828 VCO, is it correct?

    ADC12DJ5000RF EVM has multiple options for clock and if the LMK04828 is operating in just FPGA clocks out (distribution mode) and CLKin1 input frequency is same as FPGA REFCLK, it doesn't needed clock division. But if LMK04828 is using in PLL mode, it does need divider to generate required output frequency (312.5MHz).

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    TI__Expert 6180 points

    Hi Ajeet,

    Please refer to are clock diagram with GUI snapshot, 

    the SYSREF Divider and Clock Divider are all integer. 

    Below is customer tcs file for LMK04826

    LMK04826.tcs

    Thanks & Regards

    Eddie Chou

  • 0 in reply to Eddie Chou
    TI__Genius 12560 points

    Hi Eddie,

    If FPGA would need both 312.5MHz clocks (FPGA_CORECLK and FPGA_REFCLK), then both should be enable.

    Above block diagram shows, REFCLK is coming through OSCout from CLKin1 input. But configuration file doesn't set for any CLKin1 input, also OSCout is powerdown. Hence FPGA_REFCLK is not receiving any input.

    I would suggest to provide the REFCLK from any of the DCLKout (312.5M) and se the performance.

    Thanks!

    Regards,
    Ajeet Pal

  • 0 in reply to Ajeet Pal
    TI__Expert 6180 points

    Hi Ajeet,

    To speed up our debug for customer, would you support provide the correct tcs file? thanks 

    Thanks & Regards

    Eddie

  • +1 in reply to Eddie Chou
    TI__Genius 12560 points

    Hi Eddie,

    Please share the clocking connections from LMK04826 to ADC and FPGA (schematic).

    Thanks!

    Regards,
    Ajeet Pal