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CDC2351 Clock driver

vengadesh uthirapathy
Intellectual 770 points
Other Parts Discussed in Thread: CDC2351-EP, CDC2351

Hi ,

The TI clock driver  (CDC2351-EP) o/p is (0v-3.3v)LVTTL level and the i/p to this driver is from a 3.3 v I/O crystal oscillator.

The clock driver o/p is used as main system clock and given to the FPGAs,processor. But our FPGA,processor CLOCK i/p is configured as LVCMOS(0-3.3v).

 Will there be any design issues/problems due to the difference in rise and fall times for LVTTL and LVCMOS voltage levels or any other reasons

Can we directly connect the LVTTL o/p level of TI clock driver(CDC2351-EP) to LVCMOS level clock i/p pins of FPGA, processor.

Regards

Vengat

 

 

  • 0
    TI__Expert 3985 points

    Hi Vengat,

    please refer to my answer to Arvinf Raj post regarding exactly the same issue with the CDC2351:

    "the LVTTL o/p level from the CDC2351-EP are not really compatible with the typical LVCMOS i/p levels.

    Basically there is no safe margin between them. That means that the lowest LVTTL VOH (high level output voltage) is exactly equal to the LVCMOS VIH (high level input voltage) according to JEDEC standard and the same happens for VOL and VIH. It could be that this configuration may not work for some design.

    What are the output levels of your 3.3 V crystal oscillator? In case they are 3.3V LVCMOS compatible, I would rather suggest you to use the CDCLVC11xx family. It is a general purpose clock buffer family which accepts LVCMOS input and provides LVCMOS output levels.

    Please let me know if this solution fits in your system, otherwise I would look for some other one."

    Regards,

    Leandro