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CDCM7005 start-up

Karppa65
Prodigy 70 points
Other Parts Discussed in Thread: CDCM7005

Hi,

I plan to use CDCM7005 to distribute a 400 MHz clock to several boards. The boards need to be in synch, meaning that not only the input frequency must be the same, but the clocks must also start at the same time. If I initialize the control registers, and then release the /RESET-bit in the control register, will all the outputs start synchronously if they are programmed the same way? Are the clock pulses valid already just after releasing the /RESET-bit (not any glitches/bursts in the start-up)? To summarize, I need to ensure that all the target boards receive the same amount of clock pulses.

This would be a nice way to sync the boards without a separate sync signal.

Br, Karppa

  • 0
    Prodigy 70 points

    Hm, I guess /RESET is not the way to synch the outputs. Probably it is better to use the "Output YX Mode" bits of Word 1. So, after initialization, If I enable all the outputs with a single write to Word 1, will the clocks appear at the outputs YXA / YXB exactly at the same time? No extra pulses in any output?

    Br, Karppa

  • 0 in reply to Karppa65
    TI__Intellectual 950 points

    Sorry, for kept you waiting with the reply! The /RESET and OUTPU-ENABLE function of CDCM7005 working asynchron --> this may result in glitches or puls dissortions. However, the clock will appear at the same time, if all outputs are enabled (via /RESET or OUTPUT-ENABLE) simultaneously.

    Regards,

    Georg.

  • 0 in reply to Georg
    Prodigy 70 points

    Hi Georg,

    Thank you for your reply. For our application asynchronous operation is really bad news. Is there anything that could be done to make it operate synchronously, by synchronizing control inputs to input clock for example ? I guess not. Then the only solution I can see now is to use only one output of CDCM7005, and use a 1-to-4 LVPECL fanout buffer with synchronous enable to generate four identical copies of the clock.

    Br, Kari

  • 0 in reply to Karppa65
    TI__Intellectual 950 points

     Hi Kari,

    what about using a D-Typ FF to synchronize the /RESET signal to the 400MHz clock? This will be an external solution where the /RESET signal is connected to the D-Input and the 400MHz clock to the CLK input of the Flip-Flop. That avoid any glitches at the output.

    Regards,

    Georg. 

  • 0 in reply to Georg
    Prodigy 70 points

    Hi,

     

    Yes, this sounds promising. And I guess I can clock the FF with 10 MHz reference as well, as it has CMOS level. 400 MHz clock has LVPECL level. The 10 MHz reference and the 400 MHz VCXO are phase locked. The FF must be quite fast, right?

    Br, Kari

  • 0 in reply to Karppa65
    TI__Intellectual 950 points

    Hi Kari,

    good point! 400MHz might be too challaning for the FF, but 10MHz will work! And as both frequencies are phase-locked anyway, the synch should work. Pls notice, thatat power-on the PLL has some lock time (several 100ms) until both frequencies are in lock.

    Regards, Georg.