Hello to all,
My professor asked me to do a reference design using TI's TSW4200 AD/DA EVM kit and Xilinx ML605 EVM board. The reference design is to design a Dightal up-converter and a digital down-converter on Xilinx's FPGA and create a data loop with TSW4200 AD/DA EVM boards.
According to the design, I need to use cdce72010 on TSW4200ADC EVM board to generate a 61.44MHz clock for ADS62P49. I use onboard 491.52MHz VCXO and a 19.2MHz external reference clock from TSW4200DAC EVM board. And I plan to implement a SPI interface between TSW4200ADC EVM board and ML605 board to configure the cdce72010. But after several tries I just can not get the required clock from cdce72010. The clock generated by cdce72010 is always 245.76MHz.
The cdce72010's registers value are shown below (from register0 to register12):
683C0050, 68000021, 83040002, 68000003, E9800004, 68000005, 68000006, 83800017, 68000098, 68050CC9, 0C000F0A, 0000040B, 0000180C
Since I'm new to this area, any advices are welcomed.
Thank you,
Xuming Zhou
