LMK04828: Master and Slave LMK Clock Input

KLN

Part Number: LMK04828

One question on the Sinewave at LMK Input Clock standards ( i.e LVPECL Single ended Output).

We have Master and Slave LMK scheme
The master LMK will supply the clock input to all of the slave LMKs in our system of multiple LMKs (Master and Slave LMK). Through a SMA Connector, the Master sends LVPECL Output while the Slave only receives Single Ended Clock IN.
Hence Only the P output of the LVPECL will be linked to the SMA Connector at the Master, and this single ended P Output sinewave will be connected to the Slave. The negative output of the LVPECL will be terminated with a 50 Ohm termination at the Master as shown in below figure,

Please confirm above scheme.

Thanks

over 2 years ago

0 Andrea Vallenilla over 2 years ago

TI__Genius 10985 points

Hello Lakshminarayana,

I will get back to you latest Monday PST.

Thanks,

Andrea

0 Andrea Vallenilla over 2 years ago

TI__Genius 10985 points

Hello Lakshminarayana,

Your configuration should be correct. The only thing I would suggest is to remove the capacitor and 240-Ω resistor from the negative pin on your master output. Since you are terminating it with a 50-Ω resistor, those two components should not be needed. Also, would like to emphasize as well that this setup will only work if you do populate R9. If not, this logic will not be applicable.

Good Luck,

Andrea

0 KLN over 2 years ago in reply to Andrea Vallenilla

Intellectual 320 points

Which R9 resisor you're pointing?

+1 Andrea Vallenilla over 2 years ago in reply to KLN

TI__Genius 10985 points

Hello Lakshminarayana,

Please find my answer in the picture embedded below.

Good Luck,

Andrea

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LMK04828: Master and Slave LMK Clock Input