Dear Team,
Hi, I have a requirement of Phase locking 100MHz OCXO output (-130dBc@100Hz) to a High stability 10MHz Clock source.
I was looking into the below parts,
1.LMK05028
2.CDCM7005
Can you please let me know if i can make use of the above mentioned or any alternate part. What would be the connections & measured output Phase noise of such implementation?
It would be greatly helpful if you could share any application note or design for Phase locking an OCXO with a PLL.
Thanks & Regards,
Deva