Hi，
The input clock of LMK00804B is 4.8828125MHz LVDS clock with AC-couple, and it have ~50% dute cycle(yellow curve in below figure). But the dute cycle of output clock is not in the range of 45%~55%(blue curve) as mentioned in datasheet as below figure shown. why?
Thanks in advance!!!
Best regards!
Jason
Hi Jason,
LMK00804B requires a minimum common mode voltage of 0.5 V. AC coupled LVDS common mode voltage is around 0V which could be causing this issue.
For AC coupled inputs, you might need to externally DC bias the signal after decoupling caps or use DC coupled inputs.
Let me know if this fix your issue with duty cycle.
Best,
Asim
Hi, Asim:
Your suggestion fix my issue.
I replace 0.1uF capacity with 0ohm resistor. Now the dute cycle of LVCOMS output have been close to 50%. Thank you very much!
Why I use AC-couple to input clock is that I deem that CLK and nCLK have bias in the chip as below figure shown. So, it is a bad idea.
BTW, max output skew of LMK00804B is 35ps. Do you have other clock buffer to suggest to me, which have less skew than 35ps and 1 differential clock input with 4 LVCOMS output at least?
Hi Jason,
I am glad that it fixed your issue. I will take a close look at the device for any internal bias as you referred. This bias could be applicable for no clock case to keep outputs in low state. But this is just a speculation at this point until I confirm it from chip designer.
You can use LMK00105 which has maximum skew spec of 25ps. It has similar functions with five LVCMOS outputs.
Best,
Asim
Hi, Asim:
The MAX output skew of LMK00304 is 50ps, which will bring delay imbalance in super high-speed JESD204B application such as 10GSPS multi-channel acquisition system.
Do you have other clock buffer to suggest to me, which have more less output skew and 1 differential clock input with 4 differential output at least?
Thanks in advance!!!
Best regards!
Jason
