CDCM6208: Configuration problems

Hi Jiahui, 

Can you provide another image with a 500k span instead of 5 MHz with the center frequency more to the left so we can see one side band better? 
I would also need a phase noise plot please.

Regards,

Vicente 

TI support, hello!

1. Most of the time last week, we focused on the problem. At present, our company has identified the root cause of the problem. Confirm that this problem is introduced for the "10MHz" reference clock.

2. Positioning process:

1> The fault service board is newly developed, and its clock part uses the PLL chip CDCM6208 of TI.

2> The new service board cooperates with our existing three main control boards: main control board A (thermostatic crystal oscillator directly outputs 10MHz reference clock to the service board); Main control board B (thermostatic crystal oscillator+clock buffer chip Si53301 outputs 10MHz reference clock to the service board); Main control board C (thermostatic crystal oscillator+clock buffer chip CDCLVC1104 outputs 10MHz reference clock to the business board).

3> The new business board+the main control board A=OK, the new business board+the main control board C=OK, and the new business board+the main control board B=NOK (the specific fault phenomenon is described in the previous email).

4> Y4 and Y5 configured on the CDCM6028 on our business board have not passed VCO and are transmitted directly by PRI clock input. Therefore, the frequency domain characteristics of the 10MHz clock are tested from these two clock output ports. It is found that there is no significant difference between the frequency domain characteristics of the 10MHz clock and the 10MHz frequency domain characteristics output from the OK business board+main control board. Our company initially judged that the 10MHz reference clock source of the CDCM6208 is OK-------------- At the beginning, this conclusion seriously misled the orientation of our company.

5> Our company then cross verified all signals between the main control board and the business board one by one through a special exclusion positioning method (Note: since the business board can adapt to the main control boards A, B and C, because the interface definitions of the three main control boards are consistent), we finally found that the introduction point of the problem was the 10MHz reference clock sent from the main control board to the business board.

6> We modified the combination of new business board and main control board B to a certain extent, bypassed the clock buffer chip Si53301 of main control board B, and directly output the 10MHz reference clock from the thermostatic crystal oscillator to the new business board. The test was OK.

7> We tested the time domain characteristics of the 10MHz reference clock sent from the main control board to the business board at the connector under the two scenarios of the new business board+the main control board C=OK and the new business board+the main control board B=NOK, as shown in Annex 1, and found no obvious exceptions. (Note: Its overshoot and ringing phenomenon should improve a lot after the signal enters the CDCM6208, because a 22 ohm resistor is matched at the clock inlet of the CDCM6028)

3. Excuse me:

1> Main control board B (thermostatic crystal oscillator+Si53301)+new business board=OK, main control board C (thermostatic crystal oscillator+CDCLVC1104)+new business board NOK. Can we say that it is OK for TI's clock buffer+TI's clock PLL chip, and NOK for silicon's clock buffer chip+TI's clock PLL chip? Why?

2> Please provide some troubleshooting suggestions and solutions? thank you

附件1.rar

Thanks & Regards,

Jiahui

Hi Jiahui, 
I will look into more into this this week but it's possible the driver isn't meeting the TI receivers input requirements.
Can you share the driver's (Si buffer) specs/datasheet? 

Regards,

Vicente

Hi Vicente，

Thanks for your quick reply.

Here is the datasheet

Si53301.pdf

If you have other needs, please feel free to contact us.

Thanks & Regards,

Jiahui

Hi Vicente，

Cutomer replied

he problem has been solved. The problem lies in the power supply to the buffer chip of Silicon. 

Thanks for your support.

Regards,

Jiahui