LMX2491: Phase Noise Analysis

Aishwarya K V

Part Number: LMX2491

Hi,

I am trying to analyze the phase noise of the entire PLL when External VCO and Loop Filter is used and i have following queries:

1)According to theory, the phase noise of PLL will follow the OCXO (Reference Oscillator) Noise within loop bandwidth. But i am not able to see the result when i simulate LMX2491.

2) According to theoretical calculation the OCXO (100MHz), have phase noise of -155dBc/Hz @ 1KHz offset; I want to understand why PLL phase noise is not improving beyond -97dBc/Hz at 1KHz offset.

3) I am not able to load the OCXO and VCO phase noise data as the error says "Offset violates 3 point model assumption" and "The 1/f^3 noise could not be calculated".

Kindly guide me to evaluate the correctness of the design

over 3 years ago

0 Noel Fung over 3 years ago

TI__Guru** 121130 points

Hi Aishwarya,

Please use "Load Data" to upload the phase noise of your reference clock and VCO to the tool. This is the best way to get a more accurate simulation.

Attached here is an example. The left column is offset frequency in Hz.

Fullscreen CWX813 100MHz.txt Download

100	-116.5
1000	-134.7
10000	-148.2
100000	-157.2
1000000	-161.3

0 Aishwarya K V over 3 years ago in reply to Noel Fung

Prodigy 80 points

I received the suggestion and it was helpful. But my concern is the phase noise. The phase noise response is not matching according to theoretical calculation. My OCXO at 4GHz with 1KHz offset has -123dBc/Hz. But the total phase noise i am observing after simulation is not more than -93dBc/Hz. Could you give me an explanation on why this behaviour is seen.

0 Noel Fung over 3 years ago in reply to Aishwarya K V

TI__Guru** 121130 points

Hi Aishwarya,

As you can see from your sim result, at 1kHz, the phase noise is dominated by the PLL noise.

0 Aishwarya K V over 3 years ago in reply to Noel Fung

Prodigy 80 points

Hi is there any way to improve the phase noise of PLL? My requirement is overall noise at 1Khz offset at 4GHz carrier is -115dBc/Hz. I have tried all the options but i am not able to achieve it

0 Noel Fung over 3 years ago in reply to Aishwarya K V

TI__Guru** 121130 points

Hi Aishwarya,

You need to reduce the loop bandwidth to be smaller than 1kHz so that the loop filter can reduce PLL noise at this offset frequency. However, with a small loop bandwidth, the phase noise at this offset will be dominated by the VCO. Your VCO's phase noise at this offset should also be smaller than -115dBc/Hz.

In my opinion, -115dBc/Hz at 1kHz offset at 4GHz carrier is a very tough specification. I don't aware any PLL can meet this requirement.

0 Aishwarya K V over 3 years ago in reply to Noel Fung

Prodigy 80 points

Thank you for the clarification. I have one more question. How does the simulator is computing the lock time? Is it possible to display the lock time for the user either in GUI or through a display?