LMK04828: Clock output is not what I set.

Yoonsun Kim

Expert 1870 points

Part Number: LMK04828

Hi,

I set lmk04828 single loop 0-delay and changed FB_MUX_EN ald PLL2_NCLK_MUX as same value as Table 8 of datasheet.

The OSCin was 288MHz and VCO was selected as 2592MHz.

I expected 288MHz on DCLKout(Clock Divider = 9) 9MHz SDCLKout(SYSREF Divider = 288)

However, the output of DCLKout was about 296MHz and SDCLKout was about 9.26MHz

What should I do get proper output?

I attached tcs file and screen capture files.

LMK04828_oscin_single-loop_2022_1121_sysref.tcs

Regards,

over 3 years ago

0 Ajeet Pal over 3 years ago

TI__Genius 12720 points

Hi YS,

For the 0-delay mode, you can follow the Multi-LMK sync app note, which showcase the conditions/rules to follow for true 0-delay mode operation.

Table 6 and Figure 21 in the datasheet shows for the single PLL mode only not for 0-delay mode. Hence your setup will work for PLL2 mode only.

It seems, with the attached file, PLL2 is not locking and generate default VCO output. Please verify the PLL2 lock status.

Here, PLL2_N_CAL divider value should be same as PLL2_N value, as the PLL2 is calibrating with the PLL2_N_CAL value. Please see below updated config file and try it in your setup.

LMK04828_oscin_single-loop_2022_1121_sysref_updated.tcs

Thanks!

Regards,
Ajeet Pal

0 Yoonsun Kim over 3 years ago in reply to Ajeet Pal

Expert 1870 points

Hi Ajeet

I changed PLL2_N_CAL to 3 so PLL2_N value and PLL2_N_CAL had same value.

I checked the PLL2 LD is low state. I think that low state means unlock.

Do I need to change internal loop filter values? Is there any rule to select profer values?

Regards,

+1 Ajeet Pal over 3 years ago in reply to Yoonsun Kim

TI__Genius 12720 points

Hi YS,

There seems to be some settings issues in your config file.

I have created from beginning and validated in the setup, which is locking the PLL.

Please use the same and let me know if any issue. You can change the output channel dividers value for your required frequencies.

LMK04828_oscin_single-loop_288MREF_updated.tcs

Thanks!

Regards,

Ajeet Pal

0 Yoonsun Kim over 3 years ago in reply to Ajeet Pal

Expert 1870 points

Thank you Ajeet

I programmed the values you attached and checked that clocks output successfully profer frequency.

I compared two tcs files and found that PLL2 prescaler was set as 'Powerdown'.

By the way, how can I set or clear PLL2_PRE_PD bit of register 0x173 at TICS Pro software?

Regards,

YS Kim

0 Ajeet Pal over 3 years ago in reply to Yoonsun Kim

TI__Genius 12720 points

Hi YS,

You can operate PLL2_PRE_PD bit through User Controls (Power section) page or Raw register (individual register write) page in TICS Pro.

Thanks!

Regards,
Ajeet Pal

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LMK04828: Clock output is not what I set.