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LMK05028: Vdiff and Vcm specification not meeting requirement

David Huang
Intellectual 2285 points

Part Number: LMK05028
Other Parts Discussed in Thread: LMK05318B, LMK5B33216

Hi team

My customer is planning on using LMK05028 for their Agilex FPGA, but is worrying about the Vdiff and Vcm specifications on the datasheet do not meet the requirement.

Vdiff

The FPGA transceiver (F-tile) has a requirement of Vdiff＝0.6～1.7V, with LVDS VOD(250～450mV)x2 the Vdiff would be 0.5～0.9V which the minimum value does not meet the requirement.

Is it possible to modify the output current to increase the VOD value?

Vcm

The FPGA has a Vcm=0.3～1.1V requirement for the differential signal being input to the general IO pins.

However, the datasheet of LMK says VOS(Vcm)＝100～430mV which is lower than the requirement. Is there a way to modify the VOS(Vcm)?

If external circuit can be used to adjust the Vcm value, could you please advise a reference simple diagram to achieve adjusting the Vcm to around 0.6V? (In this case, the 0.6V would be generated from the 1.2V using a voltage divider)

If you have any other suggestions or advice, I'd appreciate it if you could let me know.

Regards

  • 0
    TI__Intellectual 2285 points

    Hi Team

    Adding another question:

    The figure 1 on datasheet page 3 there's phase noise specification, for the FPGA used by the customer there are requirements as below:

    10 kHz：-130dB(Typ)、100 kHz：-138dB(Typ)、500 kHz：-138dB(Typ)、3 MHz：-140dB(Typ)、10 MHz：-144dB(Typ)、20 MHz：-146dB(Typ)

    The figure doesn't include too detailed info on the noise, but I see some for 10kHz the noise doesn't seem to meet the requirement. Could you please confirm this as well?

    Regards

  • 0 in reply to David Huang
    TI__Genius 11005 points

    Hello David,

    We will get back to you!

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    TI__Genius 17025 points

    Hi David,

    I apologize for the delay--I just noticed my response didn't go through.

    Some comments and questions:

    1. Why did they choose LMK05028? I'm wondering if LMK05318B might be better option. Please provide the frequency plan outlining their required outputs and expected DPLL reference inputs.
    2. The AC output format types (e.g. AC-LVDS, AC-LVPECL, AC-CML) available on LMK05028 and LMK05318B are all based on the CML type architecture, refer to Section 9.3.13.1 of the LMK05028 datasheet. 
      1.  
      2. This means that to choose between AC-LVDS, AC-LVPECL, and AC-CML, the current is adjusted to either 4, 6, or 8 mA. With that in mind, they can use AC-CML type to meet their FPGA swing requirements which will output a swing between Vdiff＝0.8～1.6V,.
      3. Note the AC-LVDS, AC-LVPECL, and AC-CML outputs should be AC-coupled because the internal bias is CML based and will not meet the standard LVDS requirements. This is what I propose:
    3. Will these FPGA outputs be for SYSREF ? 

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    TI__Intellectual 2285 points

    Hi Jennifer

    Thanks for the response!

    The images you uploaded seem to failed loading on my end... Are they well displayed on your end? Could you try re-uploading those images?

    Also, could you please advise on phase noise as well?

    David Huang said:

    The figure 1 on datasheet page 3 there's phase noise specification, for the FPGA used by the customer there are requirements as below:

    10 kHz：-130dB(Typ)、100 kHz：-138dB(Typ)、500 kHz：-138dB(Typ)、3 MHz：-140dB(Typ)、10 MHz：-144dB(Typ)、20 MHz：-146dB(Typ)

    The figure doesn't include too detailed info on the noise, but I see some for 10kHz the noise doesn't seem to meet the requirement. Could you please confirm this as well?

    For you questions, I will confirm with the customer and get back to you!

    Regards

  • 0 in reply to David Huang
    TI__Genius 17025 points

    Hi David,

    Please have the customer share their frequency plan (inputs and outputs). Once they share it, I can comment on meeting the phase noise spec.

    I also reuploaded the images above.

    Regards,

    Jennifer

  • 0 in reply to Jennifer Bernal
    TI__Intellectual 2285 points

    Hi Jennifer

    Apologies for the delay. Below are their frequency plans

    Input:

    AC-LVDS 388.8MHz

    LVCMOS(XO) 48MHz

    Output

    AC-LVDS 644.531MHz

    AC-LVDS 155.52MHz

    AC-LVDS 161.13MHz

    AC-LVDS 156.25MHz

    LVCMOS 125.0MHz

    LVCMOS 100.0MHz

    LVCMOS 33.333MHz

  • 0 in reply to David Huang
    TI__Genius 11005 points

    Hello David,

    I will check this for you this week.

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    TI__Genius 11005 points

    Hello David,

    Since you have 4 frequency domains, you would need at least 2 parts (we don't have a single device that can generate 4 different frequency domains). I tested the phase noise profile with your output frequencies on the LMK05318B and the LMK05028 and there was no set up that were less than the the phase noise profiles you posted previously. Therefore, you have a few options:

    - Run these two configs and expect for the phase noise from the LMK05028 config to not meet the phase noise profile for offsets 100 kHz (by about -4dBc/Hz) for output frequency 155.52 MHz and for phase noise offsets 10 kHz, 100 kHz, and 500 kHz (ranging from -5 to -15 dBc/Hz difference) for output frequency 644.531 MHz. Also, at other offset frequencies the phase noise calculated was significantly to the profiles you posted. 

    5028_PhaseNoise.tcs

    5318B_PhaseNoise.tcs

    If this does not work for you, what I would suggest to use instead of the LMK05028 is the LMK5B33216 or one of our jitter cleaners (LMK048xx parts). Do note that for a jitter cleaner you would also need a VCXO. Hope this helps!

    Good luck,

    Andrea