Other Parts Discussed in Thread: CDCE6214,
For driving a GTH clock on a ZU4 IBIS model and the CDCE6214 output is running at 3V3, is it preferred to run the OUT4 output as HCSL output into the differential clock input on the Zynq or is it better to use LVDS?
I'm new to this and mostly just don't think I understand the differences or advantages of using one over the other.
My simulation (which uses an IBIS model for the driver/receiver and an s-parameter for the PCB) shows that the LVDS_3p3 driver for the CDCE6214-Q1 takes an eternity to settle out even though there appears to be better over-undershoot and potentially better rise/fall time performance (spec for GTR transceiver clocks on the ZU+ is 200ps rise/fall and V_IDIFF of 250mV-2000mV). It looks like the HCSL has a bit of non-monotonicity, but it's hard to run multiple sims because they take a day and an age to run. I still haven't had a successful run showing the LVDS_3p3 performance after it stabilizes.
Can someone point me to some resources to pick a driver or provide a source showing the differences and why one is preferred over the other?
