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LMK04828: Question about multi-chip synchronization

shen jie
Intellectual 335 points

Part Number: LMK04828

Hi, all:

I read the multi-clock SYNC app note(Multi-Clock Synchronization) carefully, which is suggested by Ajeet Pal. There is a question about case 2 of ZDM example:

As below figure.1 shown, when R' is not 1, it will bring phase uncertainty from input to output. In case 2 of ZDM example, reference frequency(60MHz) and output frequency(40MHz) are not integral multiple relation

figure.1 

As below figure.2 shown, if I change condition as following, I got N' / R' = 5 / 2 at last. So R' is not 1, which will bring phase uncertainty according to case 2. But reference frequency(60MHz) and output frequency(30MHz) are integral multiple relation(twice), So, question is if Integral multiple relation will align edge of reference frequency and output frequency? if yes, does it cause phase certainty?

Reference frequency = 60 MHz, VCO frequency = 150 MHz , Output frequency = 30 MHz, D=5, N=3

figure.2

Thanks in advance!

Best regards!!!

Jason

  • 0
    TI__Genius 10995 points

    Hello Jason,

    I'll get back to you by next week.

    Best,

    Andrea

  • 0 in reply to Andrea Vallenilla
    Intellectual 335 points

    Hi，Andrea：

    Any feedback from you? 

    Thanks in advance!

    Best regards!

    Jason

  • 0 in reply to shen jie
    TI__Genius 10995 points

    Hello Jason,

    I will get back to you by the end of the week. Thanks!

    Best,
    Andrea

  • 0
    TI__Genius 10995 points

    Hello Jason,

    To directly answer your question, you will see aligned edges of the reference frequency and output frequency but will not have phase certainty.

    I believe you are confusing phase certainty with obtaining a matching phase between your reference frequency and output frequency, one being true is not necessarily dependent of the other. Having matching phase between your reference and your outputs means that at every rising edge of your phase detector frequency you will see a rising edge in both your reference frequency and your clock output frequency (as seen in the green lines in the figure below, figure 9 in the app note you referenced).

    Having deterministic phase alignment means that on every edge of your reference clock you will see a phase-aligned VCO clock edge, as shown in the picture below by the blue dashed lines.

    Therefore, you can have alignment between your reference and your outputs and not have alignment with a VCO edge and every rising edge of your reference. If you compare the two figures above, you can see that the first figure that the reference frequency doesn't have alignment at all times with a VCO edge whenever an edges of the reference occurs. On the second figure, you can see that for every edge of the reference clock you have a phase-aligned VCO edge (this explains why you don't have phase certainty). Also, in both figures above, you can see at every green line (or whenever a phase detector frequency edge occurs), you have alignment between the output and the reference, which is what you need to lock the PLL, and therefore, have a zero-delay mode relationship (reference and output frequencies aligned). Hope this helps.

    Good Luck,

    Andrea