We use the LMK04828 to generate clocks and SYSREFs for several FPGAs and high-speed converters.in our system.
All references below are to the latest datasheet version (revised May 20).
We need to use several different SYSREF modes (and we need to be able to change between these modes during system operation).
Until now we have been using continuous SYSREF mode and SPI-triggered pulse mode, which work fine. We now need to also use external sync-triggered pulsed mode, that is we need to generate a (single) SYSREF pulse upon a transition on the SYNC/SYSREF line.
I am using the 4th configuraion in Table 1. This basically works, however I see a delay of about 300 ns between SYNC line transition and the leading edge of the SYSREF output pulse. This delay varies between 250 and 350 ns (approximately) between system restarts.
Additional information:
SYSREF frequency is 10 MHz, CDP frequency is 2560 MHz
SDCLKoutY_DDLY = 0, SDCLKoutY_HS = 0, SDCLKoutY_ADLY_EN = 0
I understand the variability in the above delay (it agrees well with 10 MHz SYSREF frequency), however I do not understand the minimum delay of 250 ns (and it causes us problems).
What is the expected delay between SYNC pin assertion and the leading edge of the (first or only) output SYSREF pulse? Is there a way to decrease it?
Note: I generate a a SYNC event during initialization per section 9.3.2.1.1 in the datasheet. I do not generate such event upon SYSREF mode change since there are no changes to the divisors or digital delays (I tried doing it, nevertheless, and it didn't help).
Thanks,
